Volume 31,
Number 1,
May 2002
Volume 31,
Number 2,
June 2002
- Michael J. Schulte, Graham A. Jullien:
Guest Editorial.
75-76
- Ohsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr.:
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells.
77-89
- H. Safiri, Majid Ahmadi, Graham A. Jullien, William C. Miller:
A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming.
91-100
- William L. Freking, Keshab K. Parhi:
Performance-Scalable Array Architectures for Modular Multiplication.
101-116
- Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh, Tobias G. Noll:
Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality.
117-126
- Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman:
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators.
127-142
- Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang:
Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers.
143-156
- Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo:
Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing.
157-171
- Wael M. Badawy, Magdy Bayoumi:
A Multiplication-Free Algorithm and A Parallel Architecture for Affine Transformation.
173-184
Volume 31,
Number 3,
July 2002
Copyright © Mon Nov 2 22:00:59 2009
by Michael Ley (ley@uni-trier.de)