The Journal of VLSI Signal Processing, Volume 12

Volume 12, Number 1, January 1996

• Wayne Luk, Duncan A. Buell:
  Guest editors' introduction. 5
  
• James B. Peterson, Peter M. Athanas:
  High-speed 2-D convolution with a custom computing machine. 7-19
  
• Laurent Moll, Jean Vuillemin, Philippe Boucard, Lars Lundheim:
  Real-time high-energy physics applications on DECPeRLe-1 programmable active memory. 21-33
  
• Matthew Aubury, Wayne Luk:
  Binomial filters. 35-50
  
• Paul Shaw, W. Paul Cockshott, Peter Barrie:
  Implementation of lattice gases using FPGAs. 51-66
  
• James G. Eldredge, Brad L. Hutchings:
  Run-Time Reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs. 67-86
  
• Ian Page:
  Constructing hardware-software systems from a single description. 87-107
  

Volume 12, Number 2, May 1996

• Maria Grazia Albanesi, Anna Antola, Marco Ferretti, Roberto M. Negrini:
  A chip-set for the Generalized Hough Transform. 115-134
  
• Jinn-Wang Yeh, Wen-Jiunn Cheng, Chein-Wei Jen:
  VASS - A VLSI array system synthesizer. 135-158
  
• Francis H. Y. Chan, Francis K. Lam, H. F. Li, J. G. Liu:
  An all adder systolic structure for fast computation of moments. 159-175
  
• Roderick McConnell, Dominique Lavenier:
  Prototyping of VLSI components from a formal specification. 177-186
  
• Karl-Heinz Zimmermann:
  Linear mappings ofn-dimensional uniform recurrences ontok-dimensional systolic arrays. 187-202
  

Volume 12, Number 3, June 1996

• Javier D. Bruguera, Nicolas Guil, Tomás Lang, Julio Villalba, Emilio L. Zapata:
  Cordic based parallel/pipelined architecture for the Hough transform. 207-221
  
• Joseph Thomas:
  Pipelined systolic architectures for DLMS adaptive filtering. 223-246
  
• Tracy C. Denk, Keshab K. Parhi:
  Lower bounds on memory requirements for statically scheduled DSP programs. 247-264
  
• Taewhan Kim, C. L. Liu:
  An integrated algorithm for incremental data path synthesis. 265-285