ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 5

Volume 5, Number 1, January 2000

• Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, J. Van Eijnhoven, Jochen A. G. Jess:
  A code-motion pruning technique for global scheduling. 1-38
  
• Wen-Jong Fang, Allen C.-H. Wu:
  Multiway FPGA partitioning by fully exploiting design hierarchy. 34-50
  
• Pao-Ann Hsiung:
  CMAPS: a cosynthesis methodology for application-oriented parallel systems. 51-81
  
• Dinesh P. Mehta, Naveed A. Sherwani:
  On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs. 82-97
  
• Sachin S. Sapatnekar, Weitong Chuang:
  Power-delay optimizations in gate sizing. 98-114
  

Volume 5, Number 2, April 2000

• Luca Benini, Giovanni De Micheli:
  System-level power optimization: techniques and tools. 115-192
  
• Jason Cong, Yean-Yow Hwang:
  Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs. 193-225
  
• Chi-Hong Hwang, Allen C.-H. Wu:
  A predictive system shutdown method for energy saving of event-driven computation. 226-241
  
• Ashok Sudarsanam, Sharad Malik:
  Simultaneous reference allocation in code generation for dual data memory bank ASIPs. 242-264
  

Volume 5, Number 3, July 2000

• Mary Jane Irwin:
  Editorial. 265-266
  
• R. Iris Bahar, Ernest T. Lampe, Enrico Macii:
  Power optimization of technology-dependent circuits based on symbolic computation of logic implications. 267-293
  
• M. Balakrishnan, Heman Khanna:
  Allocation of FIFO structures in RTL data paths. 294-310
  
• Luca Benini, Giovanni De Micheli:
  Synthesis of low-power selectively-clocked systems from high-level specification. 311-321
  
• Stephen A. Blythe, Robert A. Walker:
  Efficient optimal design space characterization methodologies. 322-336
  
• Alessandro Bogliolo, Luca Benini, Giovanni De Micheli:
  Regression-based RTL power modeling. 337-372
  
• Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski:
  Retiming-based factorization for sequential logic optimization. 373-398
  
• Vincenza Carchiolo, Michele Malgeri, Giuseppe Mangioni:
  Hardware/software synthesis of formal specifications in codesign of embedded systems. 399-432
  
• Yao-Wen Chang, Kai Zhu, D. F. Wong:
  Timing-driven routing for symmetrical array-based FPGAs. 433-450
  
• Donald S. Gelosh, Dorothy E. Setliff:
  Modeling layout tools to derive forward estimates of area and delay at the RTL level. 451-491
  
• Guy Gogniat, Michel Auguin, Luc Bianco, Alain Pegatoquet:
  A codesign back-end approach for embedded system design. 492-509
  
• Avaneendra Gupta, John P. Hayes:
  CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells. 510-547
  
• Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
  Dynamic state traversal for sequential circuit test generation. 548-565
  
• Pradip K. Jha, Nikil D. Dutt:
  High-level library mapping for memories. 566-603
  
• Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak:
  Optimizing computations for effective block-processing. 604-630
  
• David E. Long, Mahesh A. Iyer, Miron Abramovici:
  FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults. 631-657
  
• Diana Marculescu, Radu Marculescu, Massoud Pedram:
  Stochastic sequential machine synthesis with application to constrained sequence generation. 658-681
  
• Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
  On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. 682-704
  
• Richard Raimi, Ramin Hojati, Kedar S. Namjoshi:
  Environment modeling and language universality. 705-725
  
• Jin-Tai Yan:
  Three-layer bubble-sorting-based nonManhattan channel routing. 726-734
  
• Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai:
  Efficient routability check algorithms for segmented channel routing. 735-747
  

Volume 5, Number 4, October 2000

• Peter Marwedel:
  Guest Editorial. 749-751
  
• Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau:
  Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats. 752-773
  
• Koen Van Eijk, Bart Mesman, Carlos A. Alba Pinto, Qin Zhao, Marco Bekooij, Jef L. van Meerbergen, Jochen A. G. Jess:
  Constraint analysis for code generation: basic techniques and applications in FACTS. 774-793
  
• Rainer Leupers, Steven Bashford:
  Graph-based code selection techniques for embedded processors. 794-814
  
• Stefan Pees, Andreas Hoffmann, Heinrich Meyr:
  Retargetable compiled simulation of embedded processors using a machine description language. 815-834