- Pao-Ann Hsiung, Chung-Hwang Chen, Trong-Yen Lee, Sao-Jie Chen:
ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems.
- Guido Araujo, Sharad Malik:
Code generation for fixed-point DSPs.
- Giri Tiruvuri, Moon Chung:
Estimation of lower bounds in scheduling algorithms for high-level synthesis.
- Frank Vahid, Thuy Dm Le, Yu-Chin Hsu:
Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance.
- Gernot Koch, Wolfgang Rosenstiel, Udo Kebschull:
Breakpoints and breakpoint detection in source-level emulation.
- Irith Pomeranz, Sudhakar M. Reddy:
Functional test generation for delay faults in combinational circuits.
- Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi:
Structural diagnosis of interconnects by coloring.
- Dinesh P. Mehta:
Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures.
- Subhrajit Bhattacharya, Sujit Dey, Franc Brglez:
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization.
- Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Auxiliary variables for BDD-based representation and manipulation of Boolean functions.
- Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing.
- Wen-Ben Jone, K. S. Tsai:
Confidence analysis for defect-level estimation of VLSI random testing.
- Anmol Mathur, Ali Dasdan, Rajesh K. Gupta:
Rate analysis for embedded systems.
- Peichen Pan, C. L. Liu:
Optimal clock period FPGA technology mapping for sequential circuits.
- Michael A. Riepe, Karem A. Sakallah:
The edge-based design rule model revisited.
- Alan Su, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee:
Eliminating false loops caused by sharing in control path.
- Hai Zhou, D. F. Wong:
Optimal river routing with crosstalk constraints.
Copyright © Mon Nov 2 21:59:01 2009
by Michael Ley (email@example.com)
- Claudio Passerone, Claudio Sansoè, Luciano Lavagno, Patrick C. McGeer, Jonathan Martin, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli:
Modeling reactive systems in Java.
- Li-C. Wang, Magdy S. Abadir, Jing Zeng:
On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays.
- Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta:
A timing-driven design and validation methodology for embedded real-time systems.
- Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee:
ATM switch design by high-level modeling, formal verification and high-level synthesi.
- James K. Huggins, David Van Campenhout:
Specification and verification of pipelining in the ARM2 RISC microprocessor.
- David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown:
High-level design verification of microprocessors via error modeling.
- Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee:
Efficient equivalence checking of multi-phase designs using phase abstraction and retiming.
- Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
EXFI: a low-cost fault injection system for embedded microprocessor-based boards.