Transactions on High-Performance Embedded Architectures and Compilers, Volume 2, 2009

Special Section on High-Performance Embedded Architectures and Compilers

• Per Stenström, David B. Whalley:
  Introduction. 3
  
• Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras:
  Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches. 4-22
  
• Vijay Nagarajan, Rajiv Gupta, Arvind Krishnaswamy:
  Compiler-Assisted Memory Encryption for Embedded Processors. 23-44
  
• Simon Kluyskens, Lieven Eeckhout:
  Branch Predictor Warmup for Sampled Simulation through Branch History Matching. 45-64
  
• Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson:
  Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems. 65-84
  
• Chunling Hu, Daniel A. Jiménez, Ulrich Kremer:
  Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization. 85-104
  

Regular Papers

• Woojin Choi, Seok-Jun Park, Michel Dubois:
  Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors. 107-127
  
• Hans Vandierendonck, André Seznec:
  Fetch Gating Control through Speculative Instruction Window Weighting. 128-148
  
• Minwook Ahn, Yunheung Paek:
  Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers. 149-172
  
• Dominique Chanet, Javier Cabezas, Enric Morancho, Nacho Navarro, Koen De Bosschere:
  Linux Kernel Compaction through Cold Code Swapping. 173-200
  
• Aneesh Aggarwal:
  Complexity Effective Bypass Networks. 201-221
  
• Christine Rochange, Pascal Sainrat:
  A Context-Parameterized Model for Static Analysis of Execution Times. 222-241
  
• Amit Golander, Shlomo Weiss:
  Reexecution and Selective Reuse in Checkpoint Processors. 242-268
  
• Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa:
  Compiler Support for Code Size Reduction Using a Queue-Based Processor. 269-285
  
• Khaled Z. Ibrahim, Smaïl Niar:
  Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC. 286-306
  
• Patrick Mahoney, Yvon Savaria, Guy Bois, Patrice Plante:
  Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories. 307-325