IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 27

Volume 27, Number 1, January 2008

• Enrico Macii:
  Editorial. 1-2
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• Andrew B. Kahng, Kambiz Samadi:
  CMP Fill Synthesis: A Survey of Recent Studies. 3-19
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• Josep Carmona, Jordi Cortadella:
  Encoding Large Asynchronous Controllers With ILP Techniques. 20-33
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• Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi:
  Two-Dimensional Schemes for Clocking/Timing of QCA Circuits. 34-44
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• Shrirang K. Karandikar, Sachin S. Sapatnekar:
  Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem. 45-58
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• Ting Mei, Jaijeet S. Roychowdhury:
  A Time-Domain Oscillator Envelope Tracking Algorithm Employing Dual Phase Conditions. 59-69
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• Chris C. N. Chu, Yiu-Chung Wong:
  FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design. 70-83
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• Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger:
  Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards. 84-95
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• A. Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha:
  System-Level Dynamic Thermal Management for High-Performance Microprocessors. 96-108
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• Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen:
  A Reactive and Cycle-True IP Emulator for MPSoC Exploration. 109-122
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• Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras:
  Experimental Characterization of CMOS Interconnect Open Defects. 123-136
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• Irith Pomeranz, Sudhakar M. Reddy:
  Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. 137-146
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• Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Neelanjan Mukherjee, Mark Kassab:
  X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. 147-159
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• Jaskirat Singh, Sachin S. Sapatnekar:
  A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations. 160-173
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• Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy:
  Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. 174-183
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• Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
  Fixing Design Errors With Counterexamples and Resynthesis. 184-188
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• Sushanta K. Mandal, Shamik Sural, Amit Patra:
  ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs. 188-192
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• Irith Pomeranz, Sudhakar M. Reddy:
  Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits. 193-197
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• Weixin Wu, Michael S. Hsiao:
  Mining Global Constraints With Domain Knowledge for Improving Bounded Sequential Equivalence Checking. 197-201
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Volume 27, Number 2, February 2008

• Javid Jaffari, Mohab Anis:
  Variability-Aware Bulk-MOS Device Design. 205-216
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• R. Mahesh, A. Prasad Vinod:
  A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters. 217-229
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• Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma:
  Defocus-Aware Leakage Estimation and Control. 230-240
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• Ja Chun Ku, Yehea I. Ismail:
  Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies. 241-248
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• Ning Dong, Jaijeet S. Roychowdhury:
  General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations. 249-264
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• Alexander Heldring, Juan M. Rius, José Maria Tamayo, Josep Parrón:
  Compressed Block-Decomposition Algorithm for Fast Capacitance Extraction. 265-271
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• Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw:
  A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. 272-285
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• Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin:
  A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. 286-294
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• Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar:
  A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation. 295-308
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• Shantanu Dutt, Vinay Verma, Vishal Suthar:
  Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing. 309-326
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• Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker:
  On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. 327-338
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• Haralampos-G. D. Stratigopoulos, Yiorgos Makris:
  Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing. 339-351
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• Zhanglei Wang, Krishnendu Chakrabarty:
  Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns. 352-365
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• Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke:
  Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog. 366-379
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• Ilya Wagner, Valeria Bertacco, Todd M. Austin:
  Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors. 380-393
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• Hiren D. Patel, Sandeep K. Shukla:
  On Cosimulating Multiple Abstraction-Level System-Level Models. 394-398
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• Irith Pomeranz, Sudhakar M. Reddy:
  Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test. 398-403
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• Aleksandra Sesic, Stanisa Dautovic, Veljko Malbasa:
  Dynamic Power Management of a System With a Two-Priority Request Queue Using Probabilistic-Model Checking. 403-407
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Volume 27, Number 3, March 2008

• Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh:
  Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration. 409-422
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• Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
  Scalable Synthesis and Clustering Techniques Using Decision Diagrams. 423-435
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• Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, C. Negrevergne:
  Quantum Circuit Simplification and Level Compaction. 436-444
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• Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
  Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. 445-455
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• Kin Cheong Sou, Alexandre Megretski, Luca Daniel:
  A Quasi-Convex Optimization Approach to Parameterized Model Order Reduction. 456-469
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• Ngai Wong:
  Efficient Positive-Real Balanced Truncation of Symmetric Systems Via Cross-Riccati Equations. 470-480
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• Sarvesh H. Kulkarni, D. M. Sylvester, David T. Blaauw:
  Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias. 481-494
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• Baolin Yang, Yu Zhu, Ali Bouaricha, Joel Phillips:
  Applications of the Multi-Interval Chebyshev Collocation Method in RF Circuit Simulation. 495-507
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• Peter Hallschmid, Resve Saleh:
  Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs. 508-515
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• Seda Ogrenci Memik, Rajarshi Mukherjee, Min Ni, Jieyi Long:
  Optimizing Thermal Sensor Allocation for Microprocessors. 516-527
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• Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk:
  CHIPS: Custom Hardware Instruction Processor Synthesis. 528-541
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• Hristo Nikolov, Todor Stefanov, Ed F. Deprettere:
  Systematic and Automated Multiprocessor System Design, Programming, and Implementation. 542-555
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• Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar:
  An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. 556-569
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• Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda:
  An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores. 570-574
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• Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub:
  A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform. 574-578
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• Chaeho Chung, Soobum Lee, Byung Man Kwak, Gawon Kim, Joungho Kim:
  A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm. 578-583
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• Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy:
  On Complete Functional Broadside Tests for Transition Faults. 583-587
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Volume 27, Number 4, April 2008

• David Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer:
  Statistical Timing Analysis: From Basic Principles to State of the Art. 589-607
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• Patrick H. Madden, David Z. Pan:
  Guest Editorial. 608-609
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• Vishal Khandelwal, Ankur Srivastava:
  Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation. 610-620
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• Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong:
  Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. 621-632
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• Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong:
  Fast Dummy-Fill Density Analysis With Coupling Constraints. 633-642
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• Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang:
  Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. 643-653
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• Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang:
  Effective Wire Models for X-Architecture Placement. 654-658
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• Cheoljoo Jeong, Steven M. Nowick:
  Technology Mapping and Cell Merger for Asynchronous Threshold Networks. 659-672
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• Seok-Won Seong, Prabhat Mishra:
  Bitmask-Based Code Compression for Embedded Systems. 673-685
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• Ryan Fung, Vaughn Betz, William Chow:
  Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations. 686-697
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• Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew:
  GfXpress: A Technique for Synthesis and Optimization of GF(2^m) Polynomials. 698-711
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• Ying Wei, Alex Doboli:
  Structural Macromodeling of Analog Circuits Through Model Decoupling and Transformation. 712-725
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• Zhen Cao, Tong T. Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xian-Long Hong:
  Fashion: A Fast and Accurate Solution to Global Routing Problem. 726-737
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• Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen:
  Power Grid Analysis and Optimization Using Algebraic Multigrid. 738-751
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• Dmitri Maslov, Sean M. Falconer, Michele Mosca:
  Quantum Circuit Placement. 752-763
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• Neil Kettle, Andy King:
  An Anytime Algorithm for Generalized Symmetry Detection in ROBDDs. 764-777
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