Journal of Systems Architecture, Volume 49

Volume 49, Numbers 1-2, July 2003

• Peter K. K. Loh, W. J. Hsu:
  Fault-tolerance of Complete Josephus Cubes. 1-21
  
• Wu Jigang, Thambipillai Srikanthan:
  An improved reconfiguration algorithm for degradable VLSI/WSI arrays. 23-31
  
• Matthew C. Chidester, Alan D. George, Matthew A. Radlinski:
  Multiple-path execution for chip multiprocessors. 33-52
  
• Ahmad A. Hiasat, Andraos Sweidan:
  Residue number system to binary converter for the moduli set (2^n-1, 2ⁿ-1, 2ⁿ+1). 53-58
  
• Hojung Cha, Jaewook Kim, Rhan Ha:
  Erratum to "Bandwidth constrained smoothing for multimedia streaming with scheduling support" [Journal of Systems Architecture 48 (2003) 353-366]. 59
  

Volume 49, Number 3, August 2003

• Ferenc Vajda, Norbert Podhorszki:
  Parallel, distributed and network-based processing. 61-62
  
• Eladio Gutiérrez, Oscar G. Plata, Emilio L. Zapata:
  Optimization techniques for parallel irregular reductions. 63-74
  
• Manfred Feil, Andreas Uhl:
  Motion-compensated wavelet packet zerotree video coding on multicomputers. 75-87
  
• Massimo Bernaschi, Giulio Iannello, Mario Lauria:
  Efficient implementation of reduce-scatter in MPI. 89-108
  
• Frank J. Seinstra, Dennis Koelma:
  Incorporating memory layout in the modeling of message passing programs. 109-121
  

Volume 49, Numbers 4-6, September 2003

• Martyn Edwards, Lech Józwiak:
  Special-issue on reconfigurable systems. 123-125
  
• Jürgen Becker, Reiner W. Hartenstein:
  Configware and morphware going mainstream. 127-142
  
• Christophe Wolinski, Maya Gokhale, Kevin McCabe:
  Polymorphous fabric-based systems: Model, tools, applications. 143-154
  
• Kostas Masselos, Antti Pelkonen, Miroslav Cupák, Spyros Blionas:
  Realization of wireless multimedia communication systems on reconfigurable platforms. 155-175
  
• Simon Leung, Adam Postula:
  Functionally partitioned module-based programmable architecture for wireless base-band processing. 177-192
  
• Domingo Benitez:
  Performance of reconfigurable architectures for image-processing applications. 193-210
  
• Iouliia Skliarova, António de Brito Ferrari:
  The design and implementation of a reconfigurable processor for problems of combinatorial computation. 211-226
  
• Lech Józwiak, Aleksander Slusarczyk, Artur Chojnacki:
  Fast and compact sequential circuits for the FPGA-based reconfigurable systems. 227-246
  
• Lech Józwiak, Artur Chojnacki:
  Effective and efficient FPGA synthesis through general functional decomposition. 247-265
  
• Martyn Edwards, Peter Green:
  Run-time support for dynamically reconfigurable computing systems. 267-281
  
• Andrzej Krasniewski:
  Evaluation of delay fault testability of LUTs for the enhancement of application-dependent testing of FPGAs. 283-296
  

Volume 49, Numbers 7-9, October 2003

• Rajgopal Kannan, Sibabrata Ray, Radim Bartos:
  An optical switching architecture for hierarchical group communication. 297-314
  
• Coskun Mermer, Donglok Kim, Stefan G. Berg, Robert J. Gove, Yongmin Kim:
  Use of embedded DRAMs in video and image computing. 315-330
  
• Wael M. Badawy:
  A VLSI architecture for video object motion estimation using a novel 2-D hierarchical mesh. 331-344
  
• Mikel Larrea:
  On the weakest failure detector for hard agreement problems. 345-353
  
• Hun-Chen Chen, Jui-Cheng Yen:
  A new cryptography system and its VLSI realization. 355-367
  
• James Aweya, Michel Ouellette, Delfin Y. Montuno:
  A multi-queue TCP window control scheme with dynamic buffer allocation. 369-385
  
• Nadia Nedjah, Luiza de Macedo Mourelle:
  Fast reconfigurable systolic hardware for modular multiplication and exponentiation. 387-396
  

Volume 49, Numbers 10-11, November 2003

• Andrea Clematis, Daniele D'Agostino:
  Evolutions in parallel distributed and network-based processing. 397-398
  
• Marco Danelutto:
  HPC the easy way: new technologies for high performance application development and deployment. 399-419
  
• Felix Wolf, Bernd Mohr:
  Automatic performance analysis of hybrid MPI/OpenMP applications. 421-439
  
• Juan Carlos Martínez, Jose Flich, Antonio Robles, Pedro López, José Duato:
  Supporting adaptive routing in IBA switches. 441-456
  
• Schahram Dustdar, Harald Gall:
  Architectural concerns in distributed and mobile collaborative systems. 457-473
  
• Julien Bourgeois, Emmanuel Mory, François Spies:
  Video transmission adaptation on mobile devices. 475-484
  

Volume 49, Numbers 12-15, December 2003

• Martyn Edwards, Lech Józwiak:
  Preface. 485-487
  
• Krzysztof Kuchcinski, Christophe Wolinski:
  Global approach to assignment and scheduling of complex behaviors based on HCDG and constraint programming. 489-503
  
• María C. Molina, José M. Mendías, Román Hermida:
  Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources. 505-519
  
• Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst:
  Recursive bi-partitioning of netlists for large number of partitions. 521-528
  
• Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López:
  Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. 529-541
  
• D. Piso, José-Alejandro Piñeiro, Javier D. Bruguera:
  Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor. 543-555
  
• Colin Egan, Gordon L. Steven, Patrick Quick, Rubén Anguera, Fleur L. Steven, Lucian N. Vintan:
  Two-level branch prediction using neural networks. 557-570
  
• Luis Alejandro Cortés, Petru Eles, Zebo Peng:
  Modeling and formal verification of embedded systems based on a Petri net representation. 571-598
  
• Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff:
  Implementation of a streaming execution unit. 599-617
  
• Bart D. Theelen, A. C. Verschueren, V. V. Reyes Suárez, M. P. J. Stevens, A. Nuñez:
  A scalable single-chip multi-processor architecture with on-chip RTOS kernel. 619-639
  
• Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses:
  A flexible architecture for H.263 video coding. 641-661