Journal of Electronic Testing, Volume 3

Volume 3, Number 1, February 1992

John P. Robinson:
Aliasing probability transients. 9-16
Paul H. Bardell:
Discrete logarithms a parallel pseudorandom pattern generator analysis method. 17-31
Slawomir Pilarski, Kevin James Wiebe:
Counter-based compaction: An analysis for BIST. 33-43
Sungju Park, Sheldon B. Akers:
Parity bit calculation and test signal compaction for BIST applications. 45-52
D. M. Marcynuk, D. M. Miller:
The OR-k method for on-line checking of programmable logic arrays. 53-65
Chung-Len Lee, Ching Ping Wu, Wen-Zen Shen, Tyh-Song Hwang, Shueng Dar Hwang:
MT-SIM a mixed-level transition fault simulator based on parallel patterns. 67-78
Vinod Narayanan, Vijay Pitchumani:
Fault simulation on massively parallel SIMD machines algorithms, implementations and results. 79-92
Claude Thibeault, Yvon Savaria, Jean-Louis Houle:
Test quality of hierarchical defect-tolerant integrated circuits. 93-102

Vishwani D. Agrawal:
Editorial. 105
Ernst Ulrich, Karen Lentz, Jack H. Arabian, Michael Gustin, Vishwani D. Agrawal, Pier Luca Montessoro:
The Comparative and Concurrent Simulation of discrete-event experiments. 107-118
Jacob Savir, Robert F. Berry:
AC strength of a pattern generator. 119-125
Hyoung B. Min, William A. Rogers:
A test methodology for finite state machines using partial scan design. 127-137
Fabrizio Lombardi, Donatella Sciuto:
Constant testability of combinational cellular tree structures. 139-148
Dong Sam Ha, Sudhakar M. Reddy:
On the design of random pattern testable PLA based on weighted random pattern testing. 149-157
Bernhard Eschermann:
An implicitly testable boundary scan TAP controller. 159-169
James Jacob, Vishwani D. Agrawal:
Multiple fault detection in two-level multi-output circuits. 171-173
Paul H. Bardell:
Primitive polynomials of degree 301 through 500. 175-176

Janusz A. Starzyk, Hong Dai:
A decomposition approach for testing large analog networks. 181-195
Michele Favalli, Piero Olivo, Bruno Riccò:
Dynamic effects in the detection of bridging faults in CMOS ICs. 197-205
Dhamin Al-Khalili, Come Rozon, B. Stewart:
Testability analysis and fault modeling of BiCMOS circuits. 207-217
Janusz A. Brzozowski, Helmut Jürgensen:
A model for sequential machine testing and diagnosis. 219-234
Pinaki Mazumder, Janak H. Patel:
An efficient design of embedded memories and their testability analysis using Markov chains. 235-250
Bruce F. Cockburn, Janusz A. Brzozowski:
Near-optimal tests for classes of write-triggered coupling faults in RAMs. 251-264
Shyang-Tai Su, Rafic Z. Makki:
Testing of static random access memories by monitoring dynamic power supply current. 265-278

Ravi K. Gulati, Charles F. Hawkins:
Introduction. 289
Jerry M. Soden, Charles F. Hawkins, Ravi K. Gulati, Weiwei Mao:
IDDQ testing: A review. 291-303
Peter C. Maxwell, Robert C. Aitken:
IDDQ testing as a component of a test suite: The need for several fault coverage metrics. 305-316
Roger Perry:
IDDQ testing in CMOS digital ASICs. 317-325
Steven D. McEuen:
Reliability benefits of IDDQ. 327-335
J. A. Segura, Víctor H. Champac, Rosa Rodríguez-Montañés, Joan Figueras, J. A. Rubio:
Quiescent current analysis and experimentation of defective CMOS circuits. 337-348
Weiwei Mao, Ravi K. Gulati:
Quietest: A methodology for selecting IDDQ test vectors. 349-357
Chun-Hung Chen, Jacob A. Abraham:
Generation and evaluation of current and logic tests for switch-level sequential circuits. 359-366
Robert C. Aitken:
Diagnosis of leakage faults with IDDQ. 367-375
Sreejit Chakravarty, Minsheng Liu:
Algorithms for IDDQ measurement based diagnosis of bridging faults. 377-385
Josep Rius, Joan Figueras:
Proportional BIC sensor for current testing. 387-396
Wojciech Maly, Marek J. Patyra:
Design of ICs applying built-in current testing. 397-406