IEEE Design & Test of Computers, Volume 16

Volume 16, Number 1, January-March 1999

• Yervant Zorian: Focus on DRAMs. 1-

• News. 3-4

• Conference Reports. 5-

• Panel Summaries. 6-8, 90-91

• Dado Banatao: Profile of a Silicon Valley Entrepreneur. 9-15

• Robin Saxby, Peter Harrod: Test in the Emerging Intellectual Property Business. 16-18

• Bruce F. Cockburn, Fabrizio Lombardi, Fred J. Meyer: Guest Editors' Introduction: DRAM Architecture and Testing. 19-21
• Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott:
  Fault Models and Tests for a 2-Bit-per-Cell MLDRAM. 22-31
  
• Duncan G. Elliott, Michael Stumm, W. Martin Snelgrove, Christian Cojocaru, Robert McKenzie:
  Computational RAM: Implementing Processors in Memory. 32-41
  
• Bruce Millar, Peter Gillingham:
  Two High-Bandwidth Memory Bus Structures. 42-52
  
• Shinji Miyano, Katsuhiko Sato, Kenji Numata:
  Universal Test Interface for Embedded-DRAM Testing. 53-58
  
• Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang:
  A Programmable BIST Core for Embedded DRAM. 59-70
  

• Kenneth M. Butler:
  Estimating the Economic Benefits of DFT. 71-79
  
• A D&T Roundtable: Online Test. 80-86

• Mukund Modi: P1532, WAVES, and a New Initiative. 88-89

• DATC Newsletter. 93-

• TTTC Newsletter. 94-95

• Al Crouch: The DFT Psychic Network. 96-

Volume 16, Number 2, April-June 1999

• Variety at Its Best. 1-

• News. 3-4

• Mukund Modi: Mixed-Signal Test Bus, Embedded Core Test Efforts Advance. 5-6, 93

• Conference Reports. 7, 92-93

• Gordon E. Moore: A Pioneer Looks Back at Semiconductors. 8-14

• Vijay K. Madisetti: Guest Editor's Introduction: Reengineering Digital Systems. 15-16
• Ronald C. Stogdill:
  Dealing with Obsolete Parts. 17-25
  
• Gregory H. Chisholm, Steven T. Eckmann, Christopher M. Lain, Robert Veroff:
  Understanding Integrated Circuits. 26-37
  
• Vijay K. Madisetti, Yong-Kyu Jung, Moinul H. Khan, Jeongwook Kim, Theodore Finnessy:
  Reengineering Legacy Embedded Systems. 38-47
  
• Rao R. Tummala, Vijay K. Madisetti:
  System on Chip or System on Package? 48-56
  

• Manoj Sachdev, Hans G. Kerkhoff:
  Configurations for IDDQ-Testable PLAs. 58-65
  

• Xiao-Tao Chen, Wei-Kang Huang, Nohpill Park, Fred J. Meyer, Fabrizio Lombardi:
  Design Verification of FPGA Implementations. 66-73
  
• Alireza Kaviani, Stephen Dean Brown:
  The Hybrid Field-Programmable Architecture. 74-83
  

• IC Reliability and Test: What Will Deep Submicron Bring? 84-91

• Test Technology TC Newsletter. 94-95

• Scott Davidson: How Do I Boot Thee? Let Me Check Page 3. 96-

Volume 16, Number 3, July-September 1999

• Yervant Zorian: D&T Expands. 6-7

• Letter to the Editor. 8-

• News. 8-10

• Hugo De Man:
  System-on-Chip Design: Impact on Education and Research. 11-19
  

• Tony Ambler, Ben Bennetts: Guest Editors' Introduction: Test and the Product Life Cycle. 20-22
• Jon Turino:
  Design for Test and Time to Market: A Personal Perspective. 23-27
  
• Bernard Sutton:
  Board Test and the Product Life Cycle: Get Wise to Board Test. 28-33
  
• Mike Wondolowski, Ben Bennetts, Adam W. Ley:
  Boundary Scan: The Internet of Test. 34-43
  
• Bertram Weber:
  Automating PBX System Testing. 44-52
  
• Susana Stoica:
  Generating Functional Design Verification Tests. 53-63
  

• Charles F. Hawkins, Jaume Segura:
  Test and Reliability: Partners in IC Manufacturing, Part 1. 64-71
  
• Mark C. Hansen, Hakan Yalcin, John P. Hayes:
  Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering. 72-80
  
• Andreas Steininger, Christopher Temple:
  Economic Online Self-Test in the Time-Triggered Architecture. 81-89
  
• Michael Nicolaidis, Ricardo de Oliveira Duarte:
  Fault-Secure Parity Prediction Booth Multipliers. 90-101
  
• Lee Melatti, Barry Blancha:
  Testing Methodology for FireWire. 102-111
  
• A D&T Roundtable: RF Integration into CMOS and Deep-Submicron Challenges. 112-116

• Panel Summaries. 118-119

• International Mixed-Signal Testing Workshop 1999. 120-

• Mukund Modi: Status Report on Standards Affecting Design and Test. 121-122

• DATC Newsletter. 124-125

• TTTC Newsletter. 126-127

• Stephen K. Sunter: Analog, digital, and mixed-signal people. 128-

Volume 16, Number 4, October-December 1999

• Yervant Zorian: Integration Continues. 1-

• News. 5-6

• Letter to the Editor. 6-

• Terry Thomas:
  Technology for IP Reuse and Portability. 7-13
  

• Charles F. Hawkins, Jerry M. Soden: Deep Submicron CMOS Current IC Testing: Is There a Future? 14-15

• Bernard Courtois, R. D. (Shawn) Blanton: Guest Editors' Introduction. 16-17
• Tamal Mukherjee, Gary K. Fedder, R. D. (Shawn) Blanton:
  Hierarchical Design and Test of Integrated Microsystems. 18-27
  
• Salvador Mir, Benoît Charlot:
  On the Integration of Design and Test for Chips Embedding MEMS. 28-38
  
• Nicholas R. Swart:
  A Design Flow for Micromachined Electromechanical Systems. 39-47
  
• Alain Béliveau, Guy T. Spencer, Keith A. Thomas, Scott L. Roberson:
  Evaluation of MEMS Capacitive Accelerometers. 48-56
  
• Edward K. Chan, Krishna Garikipati, Robert W. Dutton:
  Comprehensive Static Characterization of Vertical Electrostatically Actuated Polysilicon Beams. 58-65
  

• Charles F. Hawkins, Jaume Segura, Jerry M. Soden, Ted Dellin:
  Test and Reliability: Partners in IC Manufacturing, Part 2. 66-73
  
• Peter J. Ashenden, Philip A. Wilsey:
  Protected Shared Variables in VHDL: IEEE Standard 1076a. 74-83
  
• Ralph Mason, Shing Ma:
  Analog DFT Using an Undersampling Technique. 84-88
  
• A D&T Roundtable: Design Automation in Europe. 90-95

• Dilip K. Bhavsar: ITC 99 Panels. 96-99

• Conference Reports. 100-101

• IEEE Design & Test of Computers 1999 Annual Index, Volume 16. 102-108

• DATC Newsletter. 109-

• TTTC Newsletter. 110-111

• Chris Rowen: Sailing on a Sea of Processors. 112-