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Yervant Zorian Vis

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*2009
171EEMark Redford, Joseph Sawicki, Prasad Subramaniam, Cliff Hou, Yervant Zorian, Kimon Michaels: DFM: don't care or competitive weapon? DAC 2009: 296-297
170EEYervant Zorian: Panel Session - Vertical integration versus disaggregation. DATE 2009: 602
169EEErik Jan Marinissen, Yervant Zorian: Guest Editors' Introduction: The Status of IEEE Std 1500. IEEE Design & Test of Computers 26(1): 6-7 (2009)
168EEErik Jan Marinissen, Yervant Zorian: IEEE Std 1500 Enables Modular SoC Testing. IEEE Design & Test of Computers 26(1): 8-17 (2009)
167EEYervant Zorian: Guest Editor's Introduction: Examples of Management Decision Criteria. IEEE Design & Test of Computers 26(2): 6-7 (2009)
2008
166EEGurgen Harutunyan, Valery A. Vardanian, Yervant Zorian: An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories. VTS 2008: 95-100
165EEAlfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian: IEEE Standard 1500 Compliance Verification for Embedded Cores. IEEE Trans. VLSI Syst. 16(4): 397-407 (2008)
2007
164EESrikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian: Making Manufacturing Work For You. DAC 2007: 107-108
163 Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian: A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories. DDECS 2007: 145-148
162EEGurgen Harutunyan, Valery A. Vardanian, Yervant Zorian: Minimal March Tests for Detection of Dynamic Faults in Random Access Memories. J. Electronic Testing 23(1): 55-74 (2007)
2006
161EERon Wilson, Yervant Zorian: Decision-making for complex SoCs in consumer electronic products. DAC 2006: 173
160EENic Mokhoff, Yervant Zorian: Tradeoffs and choices for emerging SoCs in high-end applications. DAC 2006: 273
159 Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian: Minimal March-Based Fault Location Algorithm with Partial Diagnosis for all Static Faults in Random Access Memories. DDECS 2006: 262-267
158EEGurgen Harutunyan, Valery A. Vardanian, Yervant Zorian: Minimal March Tests for Dynamic Faults in Random Access Memories. European Test Symposium 2006: 43-48
157EEGurgen Harutunyan, Valery A. Vardanian, Yervant Zorian: Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories. VTS 2006: 120-127
156EEYervant Zorian, Dennis Wassung: Session Abstract. VTS 2006: 154-155
155EEYervant Zorian, Bruce C. Kim: Session Abstract. VTS 2006: 334-335
154EEBruce C. Kim, Yervant Zorian: Guest Editors' Introduction: Big Innovations in Small Packages. IEEE Design & Test of Computers 23(3): 186-187 (2006)
2005
153EEYervant Zorian, Juan Antonio Carballo: T1: Design for Manufacturability. Asian Test Symposium 2005
152EEDennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris: Choosing flows and methodologies for SoC design. DAC 2005: 167
151EENic Mokhoff, Yervant Zorian, Kamalesh N. Ruparel, Hao Nham, Francesco Pessolano, Kee Sup Kim: How to determine the necessity for emerging solutions. DAC 2005: 274-275
150 Yervant Zorian, Bill Frerichs, Dennis Wassung, Jim Ensel, Guri Stark, Mike Gianfagna, Kamalesh N. Ruparel: Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark? DATE 2005: 572
149EEErik Jan Marinissen, Betty Prince, Doris Keitel-Schulz, Yervant Zorian: Challenges in Embedded Memory Design and Test. DATE 2005: 722-727
148EERégis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert: On-Line Testing for Secure Implementations: Design and Validation. IOLTS 2005: 211
147EEYervant Zorian, Valery A. Vardanian, K. Aleksanyan, K. Amirkhanyan: Impact of Soft Error Challenge on SoC Design. IOLTS 2005: 63-68
146EEYervant Zorian: Optimizing SoC Manufacturability. VLSI Design 2005: 37-38
145EEGurgen Harutunyan, Valery A. Vardanian, Yervant Zorian: Minimal March Tests for Unlinked Static Faults in Random Access Memories. VTS 2005: 53-59
144EEBaosheng Wang, Yuejian Wu, Josh Yang, André Ivanov, Yervant Zorian: SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms. VTS 2005: 66-71
143EEYervant Zorian: Nanoscale Design & Test Challenges. IEEE Computer 38(2): 36-39 (2005)
142EEJuan Antonio Carballo, Yervant Zorian, Raul Camposano, Andrzej J. Strojwas, John Kibarian, Dennis Wassung, Alex Alexanian, Steve Wigley, Neil Kelly: Guest Editors' Introduction: DFM Drives Changes in Design Flow. IEEE Design & Test of Computers 22(3): 200-205 (2005)
2004
141EEYervant Zorian: Investment vs. Yield Relationship for Memories in SOC. ITC 2004: 1444
140EEN. Derhacobian, Valery A. Vardanian, Yervant Zorian: Embedded Memory Reliability: The SER Challenge. MTDT 2004: 104-110
139EEBaosheng Wang, Josh Yang, James Cicalo, André Ivanov, Yervant Zorian: Reducing Embedded SRAM Test Time under Redundancy Constraints. VTS 2004: 237-242
138EESamvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian: A Methodology for Design and Evaluation of Redundancy Allocation Algorithms. VTS 2004: 249-260
137EEDon Edenfeld, Andrew B. Kahng, Mike Rodgers, Yervant Zorian: 2003 Technology Roadmap for Semiconductors. IEEE Computer 37(1): 47-56 (2004)
136EEYervant Zorian, Dimitris Gizopoulos, Cary Vandenberg, Philippe Magarshack: Guest Editors' Introduction: Design for Yield and Reliability. IEEE Design & Test of Computers 21(3): 177-182 (2004)
135EESamvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian: SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure. IEEE Design & Test of Computers 21(3): 200-207 (2004)
134 Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian: Design & Test Education in Asia. IEEE Design & Test of Computers 21(4): 331-338 (2004)
133EEIrith Pomeranz, Yervant Zorian: Fault isolation for nonisolated blocks. IEEE Trans. VLSI Syst. 12(12): 1385-1388 (2004)
132EERajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian: Distributed Diagnosis of Interconnections in SoC and MCM Designs. J. Electronic Testing 20(3): 291-307 (2004)
2003
131EEYervant Zorian: Leveraging Infrastructure IP for SoC Yield. Asian Test Symposium 2003: 3-5
130EENektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: Low-Cost Software-Based Self-Testing of RISC Processor Cores. DATE 2003: 10714-10719
129EEYervant Zorian: Yield Threats and Inadequacy of One-time Test. ITC 2003: 1284
128EENektarios Kranitis, George Xenoulis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian: Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores. ITC 2003: 431-440
127EEFrancisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, Rohit Kapur: Overview of the IEEE P1500 Standard. ITC 2003: 988-997
126EEIrith Pomeranz, Sudhakar M. Reddy, Yervant Zorian: A Test Interface for Built-In Test of Non-Isolated Scanned Cores. VTS 2003: 371-378
125 Yervant Zorian: IEEE CASS becomes D&T Copublisher. IEEE Design & Test of Computers 20(3): 108- (2003)
124 Yervant Zorian: Guest Editor's Introduction: Advances in Infrastructure IP. IEEE Design & Test of Computers 20(3): 49- (2003)
123EEYervant Zorian, Samvel K. Shoukourian: Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield. IEEE Design & Test of Computers 20(3): 58-66 (2003)
122EEAlfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian: A Hierarchical Infrastructure for SoC Test Management. IEEE Design & Test of Computers 20(4): 32-39 (2003)
121EENektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian: Instruction-Based Self-Testing of Processor Cores. J. Electronic Testing 19(2): 103-112 (2003)
120EEDimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian: Easily Testable Cellular Carry Lookahead Adders. J. Electronic Testing 19(3): 285-298 (2003)
2002
119EEYervant Zorian: Embedding infrastructure IP for SOC yield improvement. DAC 2002: 709-712
118EEIrith Pomeranz, Yervant Zorian: Fault Isolation Using Tests for Non-Isolated Blocks. DATE 2002: 1123
117EENektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian: Effective Software Self-Test Methodology for Processor Cores. DATE 2002: 592-597
116EEMichel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian: Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. DELTA 2002: 297-301
115EEValery A. Vardanian, Yervant Zorian: A March-Based Fault Location Algorithm for Static Random Access Memories. IOLTW 2002: 256-261
114EEYervant Zorian: Embedded Memory Test and Repair: Infrastructure IP for SOC Yield. ITC 2002: 340-349
113EEValery A. Vardanian, Yervant Zorian: A March-Based Fault Location Algorithm for Static Random Access Memories. MTDT 2002: 62-67
112EENektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian: Instruction-Based Self-Testing of Processor Cores. VTS 2002: 223-228
111EEAlan Allan, Don Edenfeld, William H. Joyner Jr., Andrew B. Kahng, Mike Rodgers, Yervant Zorian: 2001 Technology Roadmap for Semiconductors. IEEE Computer 35(1): 42-53 (2002)
110EEErik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian: On IEEE P1500's Standard for Embedded Core Test. J. Electronic Testing 18(4-5): 365-383 (2002)
2001
109EEYervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, Octávio Páscoa Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher: Embedded tutorial: TRP: integrating embedded test and ATE. DATE 2001: 34-37
108EEAntonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Yervant Zorian: Deterministic software-based self-testing of embedded processor cores. DATE 2001: 92-96
107EENektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. ISQED 2001: 343-349
106EEYervant Zorian: System-on-Chip: Embedded Test Strategies. ISQED 2001: 7
105 Michel Renovell, Penelope Faure, Jean Michel Portal, Joan Figueras, Yervant Zorian: IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC 2001: 924-931
104EESamvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian: An Approach for Evaluation of Redunancy Analysis Algorithms. MTDT 2001: 51-
103EEMihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian: Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. VTS 2001: 15-21
102 Yervant Zorian: Huge Storage Capacity. IEEE Design & Test of Computers 18(3): 1- (2001)
101 Yervant Zorian: Error-Free Products. IEEE Design & Test of Computers 18(4): 2- (2001)
100 Yervant Zorian: EIC Message. IEEE Design & Test of Computers 18(5): 1- (2001)
99EEKoppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian: Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures. IEEE Trans. Computers 50(10): 1007-1019 (2001)
98EERajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian: Switching activity generation with automated BIST synthesis forperformance testing of interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1143-1158 (2001)
97EENektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, Yervant Zorian: An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. J. Electronic Testing 17(2): 97-107 (2001)
96EEMichel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian: A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electronic Testing 17(3-4): 283-290 (2001)
2000
95EEMichel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian: TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium 2000: 323-328
94EETsin-Yuan Chang, Yervant Zorian: SoC Testing and P1500 Standard. Asian Test Symposium 2000: 492-
93EEYervant Zorian, Erik Jan Marinissen: System chip test: how will it impact your design? DAC 2000: 136-141
92EEYervant Zorian, Michael Nicolaidis, Peter Muhmenthaler, David Y. Lepejian, Chris W. H. Strolenberg, Kees Veelenturf: Tutorial Statement. DATE 2000: 66
91EEYervant Zorian: Yield Improvement and Repair Trade-Off for Large Embedded Memories. DATE 2000: 69-70
90EEDimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian: Effective Low Power BIST for Datapaths. DATE 2000: 757
89 Yervant Zorian, Sujit Dey, Mike Rodgers: Test of Future System-on-Chips. ICCAD 2000: 392-398
88EEYervant Zorian: Embedded-Quality for Test. ISQED 2000: 211-212
87 Yervant Zorian, Erik Jan Marinissen, Rohit Kapur: On using IEEE P1500 SECT for test plug-n-play. ITC 2000: 770-777
86 Michel Renovell, Yervant Zorian: Different experiments in test generation for XILINX FPGAs. ITC 2000: 854-862
85 Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Fabio Ricciato, Maurizio Spadari, Yervant Zorian: HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs. ITC 2000: 892-901
84 Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel: Wrapper design for embedded core test. ITC 2000: 911-920
83EEDimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian: Low Power/Energy BIST Scheme for Datapaths. VTS 2000: 23-28
82 Yervant Zorian: Flexibility and Programmability. IEEE Design & Test of Computers 17(1): 3- (2000)
81 Yervant Zorian: Embedded in this issue. IEEE Design & Test of Computers 17(2): 5-6 (2000)
80EEYervant Zorian: Wider Coverage. IEEE Design & Test of Computers 17(3): 6- (2000)
79EENektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Mihalis Psarakis, Yervant Zorian: Power-/Energy Efficient BIST Schemes for Processor Data Paths. IEEE Design & Test of Computers 17(4): 15-28 (2000)
78EEMihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays. IEEE Trans. Computers 49(10): 1083-1099 (2000)
77EEAlfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian: A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures. J. Electronic Testing 16(3): 179-184 (2000)
76EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electronic Testing 16(3): 289-299 (2000)
75EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Local Interconnect Resources of SRAM-Based FPGA's. J. Electronic Testing 16(5): 513-520 (2000)
1999
74EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium 1999: 363-368
73EEAntonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian: An Effective BIST Architecture for Fast Multiplier Cores. DATE 1999: 117-121
72EEMichael Nicolaidis, Yervant Zorian: Scaling Deeper to Submicron: On-Line Testing to the Rescue. DATE 1999: 432-
71EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE 1999: 618-622
70 Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian: HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs. ITC 1999: 1038-1044
69 Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel: Towards a standard for embedded core test: an example. ITC 1999: 616-627
68EEMihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian: An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers. VTS 1999: 252-259
67EEIrith Pomeranz, Yervant Zorian: Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic. VTS 1999: 41-48
66 Yervant Zorian, Erik Jan Marinissen, Sujit Dey: Testing Embedded-Core-Based System Chips. IEEE Computer 32(6): 52-60 (1999)
65 Yervant Zorian: Focus on DRAMs. IEEE Design & Test of Computers 16(1): 1- (1999)
64 Yervant Zorian: D&T Expands. IEEE Design & Test of Computers 16(3): 6-7 (1999)
63 Yervant Zorian: Integration Continues. IEEE Design & Test of Computers 16(4): 1- (1999)
62 Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: An Effective Built-In Self-Test Scheme for Parallel Multipliers. IEEE Trans. Computers 48(9): 936-950 (1999)
61EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGAs: Testing the Embedded RAM Modules. J. Electronic Testing 14(1-2): 159-167 (1999)
1998
60EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium 1998: 266-271
59EEYervant Zorian: System-Chip Test Strategies (Tutorial). DAC 1998: 752-757
58EET. Bogue, Michael Gössel, Helmut Jürgensen, Yervant Zorian: Built-In Self-Test with an Alternating Output. DATE 1998: 180-
57EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE 1998: 82-88
56EECecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi: Novel Technique for Testing FPGAs. DATE 1998: 89-
55EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL 1998: 139-148
54EESujit Dey, Jacob A. Abraham, Yervant Zorian: High-level design validation and test. ICCAD 1998: 3
53EERajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian: Synthesis of BIST hardware for performance testing of MCM interconnections. ICCAD 1998: 69-73
52EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-based FPGA's: testing the LUT/RAM modules. ITC 1998: 1102-1111
51EEIlyoung Kim, Yervant Zorian, Goh Komoriya, Hai Pham, Frank P. Higgins, Jim L. Lewandowski: Built in self repair for embedded high density SRAM. ITC 1998: 1112-1119
50EEYervant Zorian, Erik Jan Marinissen, Sujit Dey: Testing embedded-core based system chips. ITC 1998: 130-
49EERajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian: A distributed BIST technique for diagnosis of MCM interconnections. ITC 1998: 214-221
48EEMihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model. VTS 1998: 152-157
47 Yervant Zorian: D&T: 15th Year in Service. IEEE Design & Test of Computers 15(1): 1- (1998)
46EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Interconnect of RAM-Based FPGAs. IEEE Design & Test of Computers 15(1): 45-50 (1998)
45 Dilip K. Bhavsar, Yervant Zorian: ITC 97 Panel Sessions. IEEE Design & Test of Computers 15(1): 7, 91 (1998)
44 Meh-Ron Amerian, William D. Atwell Jr., Ian Burgess, Gary D. Fleeman, David Y. Lepejian, T. W. Williams, Farzad Zarrinfar, Yervant Zorian: A D&T Roundtable: Testing Mixed Logic and DRAM Chips. IEEE Design & Test of Computers 15(2): 86-92 (1998)
43EEDimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: Effective Built-In Self-Test for Booth Multipliers. IEEE Design & Test of Computers 15(3): 105-111 (1998)
42 Yervant Zorian: Once Again, a Super Issue. IEEE Design & Test of Computers 15(3): 3- (1998)
41 Yervant Zorian: Challenges and Options. IEEE Design & Test of Computers 15(4): 3- (1998)
40EERicardo de Oliveira Duarte, Michael Nicolaidis, Hakim Bederr, Yervant Zorian: Efficient Totally Self-Checking Shifter Design. J. Electronic Testing 12(1-2): 29-39 (1998)
39EEMichael Nicolaidis, Yervant Zorian: On-Line Testing for VLSI - A Compendium of Approaches. J. Electronic Testing 12(1-2): 7-20 (1998)
1997
38EEMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. Asian Test Symposium 1997: 254-
37EERicardo de Oliveira Duarte, Michael Nicolaidis, Hakim Bederr, Yervant Zorian: Fault-secure shifter design: results and implementations. ED&TC 1997: 335-341
36EEChristian Dufaza, Yervant Zorian: On the generation of pseudo-deterministic two-patterns test sequence with LFSRs. ED&TC 1997: 69-76
35 Yervant Zorian: Test Requirements for Embedded Core-Based Systems and IEEE P1500. ITC 1997: 191-199
34 Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian, Mihalis Psarakis: An Effective BIST Scheme for Arithmetic Logic Units. ITC 1997: 868-877
33EEJ. Borel, M. Cecchini, C. Malipeddi, Janusz Rajski, Yervant Zorian: Systems On Silicon: Design and Test Challenges. VTS 1997: 184-185
32EEMichel Renovell, Joan Figueras, Yervant Zorian: Test of RAM-based FPGA: methodology and application to the interconnect. VTS 1997: 230-237
31EEVishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian: Power Dissipation During Testing: Should We Worry About it? VTS 1997: 456-457
30 Yervant Zorian, Rajesh K. Gupta: Design and Test of Core-Based Systems on Chips. IEEE Design & Test of Computers 14(4): 14- (1997)
29EERajesh K. Gupta, Yervant Zorian: Introducing Core-Based System Design. IEEE Design & Test of Computers 14(4): 15-25 (1997)
28EEYervant Zorian: Guest Editorial. J. Electronic Testing 10(1-2): 6 (1997)
27EEYervant Zorian: Fundamentals of MCM Testing and Design-for-Testability. J. Electronic Testing 10(1-2): 7-14 (1997)
26EEYervant Zorian, Hakim Bederr: An Effective Multi-Chip BIST Scheme. J. Electronic Testing 10(1-2): 87-95 (1997)
1996
25 Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: An Effective BIST Scheme for Datapaths. ITC 1996: 76-85
24 Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian: Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates. ITC 1996: 818-827
23 Yervant Zorian, Jan Hlavicka: Guest Editors' Introduction: East Meets West. IEEE Design & Test of Computers 13(1): 5-7 (1996)
22 Kenneth D. Wagner, Yervant Zorian: EIC Message. IEEE Design & Test of Computers 13(2): 2- (1996)
21 Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov: Panel Summaries. IEEE Design & Test of Computers 13(3): 6, 110-112 (1996)
20 Gil Philips, Yervant Zorian, Charles W. Rosenthal, Bozena Kaminska: Conference Reports. IEEE Design & Test of Computers 13(3): 8, 113-144 (1996)
19 André Ivanov, Barry K. Tsuji, Yervant Zorian: Programmable BIST Space Compactors. IEEE Trans. Computers 45(12): 1393-1404 (1996)
1995
18EEDimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: An effective BIST scheme for carry-save and carry-propagate array multipliers. Asian Test Symposium 1995: 298-302
17 Fabian Vargas, Michael Nicolaidis, Yervant Zorian: An Approach for Designing Total-Dose Tolerant MCMs Based on Current Monitoring. ITC 1995: 345-354
16 Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: An Effective BIST Scheme for Booth Multipliers. ITC 1995: 824-833
15 Sreejit Chakravarty, Ramalingam Sridhar, Shambhu J. Upadhyaya, Yervant Zorian, Gil Philips, Bozena Kaminska, Bernard Courtois: Conference Reports. IEEE Design & Test of Computers 12(4): 95-97 (1995)
14EEChih-Jen Lin, Yervant Zorian, Sudipta Bhawmik: Integration of partial scan and built-in self-test. J. Electronic Testing 7(1-2): 125-137 (1995)
1994
13 A. J. van de Goor, Yervant Zorian, Ivo Schanstra: Functional Tests for Ring-Address SRAM-type FIFOs. EDAC-ETC-EUROASIC 1994: 666
12 Yervant Zorian, A. J. van de Goor, Ivo Schanstra: An Effective BIST Scheme for Ring-Address Type FIFOs. ITC 1994: 378-387
11 Cecil A. Dean, Yervant Zorian: Do You Practice Safe Tests? What We Found Out About Your Habits. ITC 1994: 887-892
10EEA. D. J. van se Goor, Yervant Zorian: Effective march algorithms for testing single-order addressed memories. J. Electronic Testing 5(4): 337-345 (1994)
1993
9 Yervant Zorian, André Ivanov: Programmable Space Compaction for BIST. FTCS 1993: 340-349
8 Harold N. Scholz, Duane R. Aadsen, Yervant Zorian: A Method for Delay Fault Self-Testing of Macrocells. ITC 1993: 253-261
7 Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik: PSBIST: A Partial-Scan Based Built-In Self-Test Scheme. ITC 1993: 507-516
1992
6 Yervant Zorian: A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan. ICCD 1992: 59-66
5 Yervant Zorian, André Ivanov: An Effective BIST Scheme for ROM's. IEEE Trans. Computers 41(5): 646-653 (1992)
4EEAndré Ivanov, Yervant Zorian: Count-based BIST compaction schemes and aliasing probability computation. IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 768-777 (1992)
1990
3 André Ivanov, Yervant Zorian: Computing the Error Escape Probability in Count-Based Compaction Schemes. ICCAD 1990: 368-371
2EEYervant Zorian, Vinod K. Agarwal: Optimizing error masking in BIST by output data modification. J. Electronic Testing 1(1): 59-71 (1990)
1984
1 Yervant Zorian, Vinod K. Agarwal: Higher Certainty of Error Coverage by Output Data Modification. ITC 1984: 140-147

Coauthor Index

1Duane R. Aadsen [8]
2Magdy S. Abadir [152]
3Jacob A. Abraham [54]
4Vinod K. Agarwal [1] [2]
5Vishwani D. Agrawal [31]
6Robert C. Aitken (Rob Aitken) [31]
7K. Aleksanyan [147]
8Alex Alexanian [142]
9Alan Allan [111]
10Meh-Ron Amerian [44]
11K. Amirkhanyan [147]
12Tom Anderson [21]
13Karim Arabi [127]
14William D. Atwell Jr. [44]
15Mark Bapst [152]
16Hakim Bederr [26] [37] [40]
17Alfredo Benso [70] [77] [85] [122] [165]
18Dilip K. Bhavsar [45]
19Sudipta Bhawmik [7] [14]
20T. Bogue [58]
21J. Borel [33]
22J. Braden [31]
23Luca Breveglieri [148]
24Ian Burgess [44]
25Raul Camposano [142]
26Juan Antonio Carballo [142] [153]
27Stefano Di Carlo [85] [122] [165]
28Silvia Cataldo [70] [77]
29M. Cecchini [33]
30Sreejit Chakravarty [15]
31Tsin-Yuan Chang [94]
32Abhijit Chatterjee [24] [49] [53] [98] [99] [132]
33Silvia Chiusano [70] [77] [85]
34James Cicalo [139]
35Bernard Courtois [15]
36Francisco DaSilva [127]
37Debesh Kumar Das (Debesh K. Das) [134]
38Cecil A. Dean [11]
39N. Derhacobian [140]
40Sujit Dey [50] [54] [66] [89]
41Octávio Páscoa Dias [109]
42Ricardo de Oliveira Duarte [37] [40]
43Christian Dufaza [36]
44Don Edenfeld [111] [137]
45Jim Ensel [150]
46Penelope Faure [95] [96] [105] [116]
47Joan Figueras [31] [32] [38] [46] [52] [55] [56] [57] [60] [61] [71] [74] [75] [76] [95] [96] [105]
48Gary D. Fleeman [44]
49Bill Frerichs [150]
50Hideo Fujiwara [134]
51Mike Gianfagna [150]
52Dimitris Gizopoulos [16] [18] [25] [34] [43] [48] [62] [68] [73] [78] [79] [83] [90] [97] [103] [107] [108] [112] [117] [120] [121] [128] [130] [136]
53Sandeep Kumar Goel [84]
54A. D. J. van se Goor [10]
55A. J. van de Goor [12] [13]
56Michael Gössel [58]
57Steve Griffith [164]
58Rajesh K. Gupta (Rajesh Gupta) [29] [30]
59Colin Harris [152]
60Gurgen Harutunyan [145] [157] [158] [159] [162] [163] [166]
61Frank P. Higgins [51]
62Jan Hlavicka [23]
63Cliff Hou [171]
64André Ivanov [3] [4] [5] [9] [19] [21] [139] [144]
65William H. Joyner Jr. [111]
66Helmut Jürgensen [58]
67Andrew B. Kahng [111] [137]
68Bozena Kaminska [15] [20]
69Rohit Kapur [69] [87] [110] [127]
70Doris Keitel-Schulz [149]
71Neil Kelly [142]
72John Kibarian [142]
73Bruce C. Kim [154] [155]
74Ilyoung Kim [51]
75Kee Sup Kim [151]
76Goh Komoriya [51]
77Nektarios Kranitis [73] [79] [83] [90] [97] [103] [107] [108] [112] [117] [121] [128] [130]
78S. Kumar [31]
79David Y. Lepejian [44] [92]
80Régis Leveugle [148]
81Jim L. Lewandowski [51]
82Yungang Li [134]
83Chih-Jen Lin [7] [14]
84Maurice Lousberg [84] [110]
85Robert Madge [164]
86Philippe Magarshack [136]
87C. Malipeddi [33]
88Erik Jan Marinissen [50] [66] [69] [84] [87] [93] [110] [149] [168] [169]
89Teresa L. McLaurin [110]
90Cecilia Metra [56]
91Kimon Michaels [171]
92Yinghua Min [134]
93G. Mojoli [56]
94Nic Mokhoff [151] [160]
95Peter Muhmenthaler [92] [109]
96Walter Ng [164]
97Hao Nham [151]
98Michael Nicolaidis [17] [37] [39] [40] [72] [92]
99André K. Nieuwland [148]
100Ankush Oberai [164]
101Antonis M. Paschalis [16] [18] [25] [34] [43] [48] [62] [68] [73] [78] [79] [83] [90] [97] [103] [107] [108] [112] [117] [120] [121] [128] [130]
102Sandro Pastore [56]
103Rajesh Pendurkar [49] [53] [98] [132]
104Carlos Eduardo Pereira [109]
105Francesco Pessolano [151]
106Hai Pham [51]
107Gil Philips [15] [20]
108Irith Pomeranz [67] [118] [126] [133]
109Jean Michel Portal [38] [46] [52] [55] [56] [57] [60] [61] [71] [74] [75] [76] [95] [96] [105]
110Betty Prince [149]
111Paolo Prinetto [70] [77] [85] [109] [116] [122] [165]
112Mihalis Psarakis [34] [48] [68] [73] [78] [79] [83] [90] [97] [103] [107] [108] [120]
113Ruchir Puri [164]
114W. Radermacher [109]
115Janusz Rajski [33]
116Sudhakar M. Reddy [126]
117Mark Redford [171]
118Michel Renovell [32] [38] [46] [52] [55] [56] [57] [60] [61] [71] [74] [75] [76] [86] [95] [96] [105] [116]
119Mike Ricchetti [110]
120Fabio Ricciato [85]
121Mike Rodgers [89] [111] [137]
122Charles W. Rosenthal [20]
123Klaus Rothbart [148]
124Kamalesh N. Ruparel [150] [151]
125Davide Salvi [56]
126Koppolu Sasidhar [24] [99]
127Yvon Savaria [21]
128Joseph Sawicki [171]
129Ivo Schanstra [12] [13]
130Harold N. Scholz [8]
131Giacomo R. Sechi [56]
132Jean-Pierre Seifert [148]
133Jorge Semião [109]
134Samvel K. Shoukourian [104] [123] [135] [138]
135Maurizio Spadari [85]
136Ramalingam Sridhar [15]
137Guri Stark [150]
138Andrzej J. Strojwas [142]
139Chris W. H. Strolenberg [92]
140Prasad Subramaniam [171]
141Tony Taylor [69]
142Isabel C. Teixeira [109]
143João Paulo Teixeira [109]
144Claude Thibeault [21]
145Barry K. Tsuji [19]
146Shambhu J. Upadhyaya [15]
147Cary Vandenberg [136]
148Valery A. Vardanian [104] [113] [115] [135] [138] [140] [145] [147] [157] [158] [159] [162] [163] [166]
149Fabian Vargas [17]
150Kees Veelenturf [92]
151Srikanth Venkataraman [164]
152Kenneth D. Wagner [22]
153Baosheng Wang [139] [144]
154Dennis Wassung [142] [150] [152] [156]
155Lee Whetsel [69] [127]
156Steve Wigley [142]
157T. W. Williams [44]
158Ron Wilson [161]
159Yuejian Wu [144]
160Hans-Joachim Wunderlich [31]
161George Xenoulis [128] [130]
162Shiyi Xu [134]
163Josh Yang [139] [144]
164Greg Yeric [164]
165Farzad Zarrinfar [44]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)