| * | 2009 |
|---|
| 4 | EE | Thomas Edison Yu,
Tomokazu Yoneda,
Krishnendu Chakrabarty,
Hideo Fujiwara:
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints.
ASP-DAC 2009: 793-798 |
| 2008 |
|---|
| 3 | EE | Thomas Edison Yu,
Tomokazu Yoneda,
Krishnendu Chakrabarty,
Hideo Fujiwara:
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips.
IEICE Transactions 91-D(10): 2440-2448 (2008) |
| 2 | EE | Thomas Edison Yu,
Tomokazu Yoneda,
Danella Zhao,
Hideo Fujiwara:
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints.
IEICE Transactions 91-D(3): 807-814 (2008) |
| 2007 |
|---|
| 1 | EE | Thomas Edison Yu,
Tomokazu Yoneda,
Danella Zhao,
Hideo Fujiwara:
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints.
VTS 2007: 369-374 |
