Hannah Honghua Yang

2007
23	EE	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng: Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 645-658 (2007)
22	EE	Hsun-Cheng Lee, Yao-Wen Chang, Hannah Honghua Yang: MBast-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1430-1444 (2007)
2006
21	EE	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng: Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD 2006: 178-185
20	EE	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani: Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. ACM Trans. Design Autom. Electr. Syst. 11(2): 325-345 (2006)
2005
19	EE	Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong: Microarchitecture evaluation with floorplanning and interconnect pipelining. ASP-DAC 2005: 8-15
18	EE	Guowu Yang, Xiaoyu Song, Hannah Honghua Yang, Fei Xie: A Theoretical Upper Bound for IP-Based Floorplanning. COCOON 2005: 411-419
2004
17		Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu: Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. ISCAS (5) 2004: 81-84
16	EE	Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang: Constrained floorplanning using network flows. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 572-580 (2004)
2003
15	EE	Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang: Multilevel floorplanning/placement for large-scale modules using B*-trees. DAC 2003: 812-817
14	EE	Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang: Constrained "Modern" Floorplanning. ISPD 2003: 128-135
13	EE	Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani: Integrated floorplanning with buffer/channel insertion for bus-based designs. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 730-741 (2003)
2002
12	EE	Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani: Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. ISPD 2002: 56-61
2001
11	EE	Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang: Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ACM Great Lakes Symposium on VLSI 2001: 62-67
10	EE	Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 800-807 (2001)
2000
9	EE	Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: Slicing floorplans with range constraint. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 272-278 (2000)
1999
8	EE	Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani: Integrated floorplanning and interconnect planning. ICCAD 1999: 354-357
7	EE	Jeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman: Logic Verification of Very Large Circuits Using Shark. VLSI Design 1999: 310-317
6	EE	Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: Slicing floorplans with boundary constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1385-1389 (1999)
1998
5	EE	Hannah Honghua Yang, Martin D. F. Wong: Optimal min-area min-cut replication in partitioned circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1175-1183 (1998)
1997
4	EE	Hannah Honghua Yang, Martin D. F. Wong: Circuit clustering for delay minimization under area and pin constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 976-986 (1997)
1996
3	EE	Hannah Honghua Yang, Martin D. F. Wong: Balanced partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1533-1540 (1996)
1995
2	EE	Hannah Honghua Yang, D. F. Wong: New algorithms for min-cut replication in partitioned circuits. ICCAD 1995: 216-222
1994
1	EE	Hannah Honghua Yang, D. F. Wong: Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. ICCAD 1994: 150-155

Coauthor Index

1	Jinian Bian	[20] [21] [23]
2	Yici Cai	[17]
3	Jeremy Casas	[7]
4	Yao-Wen Chang	[15] [22]
5	Hung-Ming Chen	[8] [11]
6	Chung-Kuan Cheng	[21] [23]
7	Malgorzata Chrzanowska-Jeske	[12] [13]
8	Jason Cong	[19]
9	Yan Feng	[14] [16]
10	Xianlong Hong	[17] [20] [21] [23]
11	Jer-Ming Hsu	[15]
12	Ashok Jagannathan	[19]
13	Marcin Jeske	[13]
14	Mandar Joshi	[7]
15	Manpreet Khaira	[7]
16	Kris Konigsfeld	[19]
17	Hsun-Cheng Lee	[15] [22]
18	Zhuoyuan Li	[20] [21] [23]
19	Yongqiang Lu	[17]
20	Wai-Kei Mak	[11]
21	Dinesh P. Mehta	[14] [16]
22	Dan Milliron	[19]
23	Mosur Mohan	[19]
24	Steve W. Otto	[7]
25	Vijay Pitchumani	[20] [21] [23]
26	Faran Rafiq	[12] [13]
27	Glenn Reinman	[19]
28	Michail Romesis	[19]
29	Erik Seligman	[7]
30	Naveed A. Sherwani	[8] [12] [13]
31	Xiaoyu Song	[18]
32	Thomas Tetzlaff	[7]
33	Martin D. F. Wong (D. F. Wong)	[1] [2] [3] [4] [5] [6] [8] [9] [10] [11]
34	Fei Xie	[18]
35	Changqi Yang	[17]
36	Guowu Yang	[18]
37	Evangeline F. Y. Young (F. Y. Young, Fung Yu Young)	[6] [8] [9] [10]
38	Wenjian Yu	[23]
39	Shan Zeng	[21] [23]
40	Hai Zhou	[8]
41	Qiang Zhou	[17] [20] [21] [23]

Colors in the list of coauthors