| |
| 2005 | ||
|---|---|---|
| 5 | Akira Yamawaki, Masahiko Iwane: An efficient parallel processing using a cache memory with synchronization on a Soc-multiprocessor. Circuits, Signals, and Systems 2005: 142-147 | |
| 4 | EE | Akira Yamawaki, Masahiko Iwane: Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor. ISPAN 2005: 324-333 |
| 2004 | ||
| 3 | Akira Yamawaki, Masahiko Iwane: Evaluation of mechanisms introduced to improve performance of TSVM cache. Parallel and Distributed Computing and Networks 2004: 502-507 | |
| 2002 | ||
| 2 | EE | Akira Yamawaki, Masahiko Iwane: Organization of Shared Memory with Synchronization for Multiprocessor-on-a-chip. ICPADS 2002: 83-90 |
| 2001 | ||
| 1 | EE | Masahiko Iwane, Akira Yamawaki, Makoto Tanaka: Tagged communication and synchronization memory for multiprocessor-on-a-chip. Systems and Computers in Japan 32(4): 1-13 (2001) |
| 1 | Masahiko Iwane | [1] [2] [3] [4] [5] |
| 2 | Makoto Tanaka | [1] |