Kazuharu Yamato

2004
23	EE	Naotake Kamiura, Teijiro Isokawa, Kazuharu Yamato, Nobuyuki Matsui: On Retrieval of Lost Functions for Feedforward Neural Networks Using Re-Learning. KES 2004: 491-497
2002
22	EE	Naotake Kamiura, Kazuharu Yamato, Teijiro Isokawa, Nobuyuki Matsui: Learning-Based On-Line Testing in Feedforward Neural Networks. IOLTW 2002: 180
2001
21	EE	Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui, Kazuharu Yamato: On-Line Multiple-Fault-Detection of Fuzzy Controllers. IOLTW 2001: 202-
2000
20	EE	Takahiro Hozumi, Osamu Kakusho, Kazuharu Yamato: An Evolutionary Computing Approach to Multilevel Logic Synthesis Using Various Logic Operations. ISMVL 2000: 259-264
1998
19	EE	Naotake Kamiura, Yutaka Hata, Kazuharu Yamato: On Concurrent Tests of Fuzzy Controllers. ISMVL 1998: 356-
1997
18	EE	Yutaka Hata, Naotake Kamiura, Kazuharu Yamato: Multiple-Valued Product-of-Sums Expression with Truncated Sum. ISMVL 1997: 103-
17	EE	T. Utsumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato: Multiple-Valued Programmable Logic Arrays with Universal Literals. ISMVL 1997: 163-168
16	EE	Yutaka Hata, Kiyoshi Hayase, Takahiro Hozumi, Naotake Kamiura, Kazuharu Yamato: Multiple-Valued Logic Minimization by Genetic Algorithms. ISMVL 1997: 97-102
1996
15	EE	Naotake Kamiura, Yutaka Hata, Kazuharu Yamato: On Design of Fail-Safe Cellular Arrays. Asian Test Symposium 1996: 107-112
1995
14	EE	Naotake Kamiura, Yutaka Hata, Kazuharu Yamato: A cellular array designed from a Multiple-valued Decision Diagram and its fault tests. Asian Test Symposium 1995: 20-
13	EE	Yutaka Hata, Naotake Kamiura, Kazuharu Yamato: On Input Permutation Technique for Multiple-Valued Logic Synthesis. ISMVL 1995: 170-
12	EE	Takahiro Hozumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato: Multiple-Valued Logic Design Using Multiple-Valued EXOR. ISMVL 1995: 290-295
1994
11		Naotake Kamiura, Yutaka Hata, Kazuharu Yamato: Design of Fault-Tolerant Cellular Arrays on Multiple-Valued Logic. ISMVL 1994: 297-304
10		Yutaka Hata, Kazuharu Yamato: A Multiple-Valued Logic Synthesis Using the Kleenean Coefficients. ISMVL 1994: 52-57
1993
9		Kiyotaka Miyai, Yutaka Hata, Kazuharu Yamato: A Representation of Approximate Reasoning with Analogy. ISMVL 1993: 184-189
8		Yutaka Hata, Kazuharu Yamato: Multiple-Valued Logic Functions Represented by TSUM, TPRODUCT, NOT and Variables. ISMVL 1993: 222-227
7		Yutaka Hata, Takahiro Hozumi, Kazuharu Yamato: Gate Model Networks for Minimization of Multiple-Valued Logic Functions. ISMVL 1993: 29-34
6		Naotake Kamiura, Yutaka Hata, Kazuharu Yamato: A Repairable and Diagnosable Cellular Array on Multiple-Valued Logic. ISMVL 1993: 92-97
5		Yutaka Hata, Kyoichi Nakashima, Kazuharu Yamato: Some Fundamental Properties of Multiple-Valued Kleenean Functions and Determination of Their Logic Formulas. IEEE Trans. Computers 42(8): 950-961 (1993)
1992
4		Naotake Kamiura, Yutaka Hata, Fujio Miyawaki, Kazuharu Yamato: Easily Testable Multiple-Valued Cellular Arrays. ISMVL 1992: 36-42
3		Yutaka Hata, Fujio Miyawaki, Kazuharu Yamato: Optimal Output Assignment and the Maximum Number of Implicants Needed to Cover the Multiple-Valued Logic Functions. ISMVL 1992: 389-395
1991
2		Yutaka Hata, Masaharu Yuhara, Fujio Miyawaki, Kazuharu Yamato: On the Complexity of Enumerations for Multiple-Valued Kleenean Functions and Unate Functions. ISMVL 1991: 55-62
1990
1		Yutaka Hata, Kyoichi Nakashima, Kazuharu Yamato: Some Relationships Between Multiple-Valued Kleenean Functions and Ternary Input Multiple-Valued Output Functions. ISMVL 1990: 410-417

Coauthor Index

1	Yutaka Hata	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
2	Kiyoshi Hayase	[16]
3	Takahiro Hozumi	[7] [12] [16] [20]
4	Teijiro Isokawa	[21] [22] [23]
5	Osamu Kakusho	[20]
6	Naotake Kamiura	[4] [6] [11] [12] [13] [14] [15] [16] [17] [18] [19] [21] [22] [23]
7	Nobuyuki Matsui	[21] [22] [23]
8	Kiyotaka Miyai	[9]
9	Fujio Miyawaki	[2] [3] [4]
10	Kyoichi Nakashima	[1] [5]
11	T. Utsumi	[17]
12	Masaharu Yuhara	[2]