| |
| * | 2009 | |
|---|---|---|
| 4 | EE | Avi Yadgar, Orna Grumberg, Assaf Schuster: Hybrid BDD and All-SAT Method for Model Checking. Languages: From Formal to Natural 2009: 228-244 |
| 2008 | ||
| 3 | EE | Hana Chockler, Orna Grumberg, Avi Yadgar: Efficient Automatic STE Refinement Using Responsibility. TACAS 2008: 233-248 |
| 2007 | ||
| 2 | EE | Orna Grumberg, Assaf Schuster, Avi Yadgar: 3-Valued Circuit SAT for STE with Automatic Refinement. ATVA 2007: 457-473 |
| 2004 | ||
| 1 | EE | Orna Grumberg, Assaf Schuster, Avi Yadgar: Memory Efficient All-Solutions SAT Solver and Its Application for Reachability Analysis. FMCAD 2004: 275-289 |
| 1 | Hana Chockler | [3] |
| 2 | Orna Grumberg | [1] [2] [3] [4] |
| 3 | Assaf Schuster | [1] [2] [4] |