Qiang Xu

2008
24	EE	Shan Tang, Qiang Xu: A debug probe for concurrently debugging multiple embedded cores and inter-core transactions in NoC-based systems. ASP-DAC 2008: 416-421
23	EE	Jia Li, Qiang Xu, Yu Hu, Xiaowei Li: On reducing both shift and capture power for scan-based testing. ASP-DAC 2008: 653-658
22	EE	Jia Li, Qiang Xu, Yu Hu, Xiaowei Li: Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction. DELTA 2008: 26-31
21	EE	Sukhdeep Sodhi, Jaspal Subhlok, Qiang Xu: Performance prediction with skeletons. Cluster Computing 11(2): 151-165 (2008)
2007
20	EE	Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty: SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects. DAC 2007: 676-681
19	EE	Shan Tang, Qiang Xu: A multi-core debug platform for NoC-based systems. DATE 2007: 870-875
18	EE	Xiucheng Dong, Haibin Wang, Qiang Xu, Xiaoxiao Zhao: Research on Applications of a New-Type Fuzzy-Neural Network Controller. LSMS (1) 2007: 679-687
17	EE	Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty: Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1539-1547 (2007)
2006
16	EE	Qiang Xu, Baosheng Wang, F. Y. Young: Retention-Aware Test Scheduling for BISTed Embedded SRAMs. European Test Symposium 2006: 83-88
15	EE	Qiang Xu, Nicola Nicolici: DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs. IEEE Trans. Computers 55(4): 470-485 (2006)
14	EE	Qiang Xu, Nicola Nicolici: Multifrequency TAM design for hierarchical SOCs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 181-196 (2006)
2005
13	EE	Ho Fai Ko, Qiang Xu, Nicola Nicolici: Register-transfer level functional scan for hierarchical designs. ASP-DAC 2005: 1172-1175
12	EE	Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty: Multi-frequency wrapper design and optimization for embedded cores under average power constraints. DAC 2005: 123-128
11	EE	Qiang Xu, Jaspal Subhlok: Automatic clustering of grid nodes. GRID 2005: 227-233
10	EE	Qiang Xu, Nicola Nicolici: Modular and rapid testing of SOCs with unwrapped logic blocks. IEEE Trans. VLSI Syst. 13(11): 1275-1285 (2005)
9	EE	Qiang Xu, Nicola Nicolici: Wrapper design for multifrequency IP cores. IEEE Trans. VLSI Syst. 13(6): 678-685 (2005)
8	EE	Qiang Xu, Nicola Nicolici: Modular SOC testing with reduced wrapper count. IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1894-1908 (2005)
2004
7	EE	Qiang Xu, Nicola Nicolici: Multi-Frequency Test Access Mechanism Design for Modular SOC Testing. Asian Test Symposium 2004: 2-7
6	EE	Qiang Xu, Nicola Nicolici: Wrapper Design for Testing IP Cores with Multiple Clock Domains. DATE 2004: 416-421
5	EE	Qiang Xu: Content Management and Resources Integration: A Practice in Shanghai Digital Library. ICADL 2004: 25-34
4	EE	Qiang Xu, Nicola Nicolici: Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores. ITC 2004: 1196-1202
2003
3	EE	Qiang Xu, Nicola Nicolici: Delay Fault Testing of Core-Based Systems-on-a-Chi. DATE 2003: 10744-10752
2	EE	Bai Hong Fang, Qiang Xu, Nicola Nicolici: Hardware/Software Co-testing of Embedded Memories in Complex SOCs. ICCAD 2003: 599-606
1	EE	Qiang Xu, Nicola Nicolici: On Reducing Wrapper Boundary Register Cells in Modular SOC Testing. ITC 2003: 622-631

Coauthor Index

1	Krishnendu Chakrabarty	[12] [17] [20]
2	Xiucheng Dong	[18]
3	Bai Hong Fang	[2]
4	Yu Hu	[22] [23]
5	Ho Fai Ko	[13]
6	Jia Li	[22] [23]
7	Xiaowei Li	[22] [23]
8	Nicola Nicolici	[1] [2] [3] [4] [6] [7] [8] [9] [10] [12] [13] [14] [15] [17]
9	Sukhdeep Sodhi	[21]
10	Jaspal Subhlok	[11] [21]
11	Shan Tang	[19] [24]
12	Baosheng Wang	[16]
13	Haibin Wang	[18]
14	Evangeline F. Y. Young (F. Y. Young, Fung Yu Young)	[16]
15	Yubin Zhang	[20]
16	Xiaoxiao Zhao	[18]

Colors in the list of coauthors