| 2005 |
|---|
| 8 | EE | Ming Shae Wu,
Chung-Len Lee,
Yeong-Jar Chang,
Wen Ching Wu:
Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle.
Asian Test Symposium 2005: 106-111 |
| 2004 |
|---|
| 7 | EE | Chin-Lung Su,
Rei-Fu Huang,
Cheng-Wen Wu,
Chien-Chung Hung,
Ming-Jer Kao,
Yeong-Jar Chang,
Wen Ching Wu:
MRAM Defect Analysis and Fault Modeli.
ITC 2004: 124-133 |
| 6 | EE | Li-Ming Denq,
Rei-Fu Huang,
Cheng-Wen Wu,
Yeong-Jar Chang,
Wen Ching Wu:
A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.
MTDT 2004: 65-69 |
| 1998 |
|---|
| 5 | EE | Wen Ching Wu,
Chung-Len Lee,
Jwu E. Chen:
A Two-Phase Fault Simulation Scheme for Sequential Circuits.
J. Inf. Sci. Eng. 14(3): 669-686 (1998) |
| 1997 |
|---|
| 4 | EE | Chih Wei Hu,
Chung-Len Lee,
Wen Ching Wu,
Jwu E. Chen:
Fault diagnosis of odd-even sorting networks.
Asian Test Symposium 1997: 288- |
| 1995 |
|---|
| 3 | EE | Wen Ching Wu,
Chung-Len Lee,
Jwu E. Chen:
Identification of robust untestable path delay faults.
Asian Test Symposium 1995: 229- |
| 1994 |
|---|
| 2 | | Wen Ching Wu,
Chung-Len Lee,
Jwu E. Chen,
Won Yih Lin:
Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning.
EDAC-ETC-EUROASIC 1994: 661 |
| 1991 |
|---|
| 1 | EE | Wen Ching Wu,
Chung-Len Lee:
A Probabilistic Testability Measure for Delay Faults.
DAC 1991: 440-445 |
