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Martin D. F. Wong Vis

D. F. Wong

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*2009
273EELijuan Luo, Martin D. F. Wong: On using SAT to ordered escape problems. ASP-DAC 2009: 594-599
272EEHui Kong, Tan Yan, Martin D. F. Wong: Automatic bus planner for dense PCBs. DAC 2009: 326-331
271EETan Yan, Martin D. F. Wong: A correct network flow model for escape routing. DAC 2009: 332-335
270EEJia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang: Flip-chip routing with unified area-I/O pad assignments for package-board co-design. DAC 2009: 336-339
269EEPo-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang: Thermal-driven analog placement considering device matching. DAC 2009: 593-598
268EETan Yan, Martin D. F. Wong: Theories and algorithms on single-detour routing for untangling twisted bus. ACM Trans. Design Autom. Electr. Syst. 14(3): (2009)
267EEHuaizhi Wu, Martin D. F. Wong: Incremental Improvement of Voltage Assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 217-230 (2009)
266EEMuhammet Mustafa Ozdal, Martin D. F. Wong: Archer: A History-Based Global Routing Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 528-540 (2009)
2008
265EELijuan Luo, Martin D. F. Wong: Ordered escape routing based on Boolean satisfiability. ASP-DAC 2008: 244-249
264EEQuang Dinh, Deming Chen, Martin D. F. Wong: Efficient ASIP design for configurable processors with fine-grained resource sharing. FPGA 2008: 99-106
263EETan Yan, Martin D. F. Wong: BSG-Route: a length-matching router for general topology. ICCAD 2008: 499-505
262EEYu Zhong, Martin D. F. Wong: Thermal-Aware IR Drop Analysis in Large Power Grid. ISQED 2008: 194-199
261EEHannah Honghua Yang, Martin D. F. Wong: Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach. Encyclopedia of Algorithms 2008
260EELei Cheng, Deming Chen, Martin D. F. Wong: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008)
259EEHuaizhi Wu, Martin D. F. Wong, Wilsin Gosti: Postplacement voltage assignment under performance constraints. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
258EEMuhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger: Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules. ACM Trans. Design Autom. Electr. Syst. 13(4): (2008)
257EEMuhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger: Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 84-95 (2008)
256EEHua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong: Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 621-632 (2008)
255EEHua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong: Fast Dummy-Fill Density Analysis With Coupling Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 633-642 (2008)
254EELei Cheng, Deming Chen, Martin D. F. Wong: DDBDD: Delay-Driven BDD Synthesis for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1203-1213 (2008)
2007
253EELiang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang: Coupling-aware Dummy Metal Insertion for Lithography. ASP-DAC 2007: 13-18
252EEDavid M. Pawlowski, Liang Deng, Martin D. F. Wong: Fast and Accurate OPC for Standard-Cell Layouts. ASP-DAC 2007: 7-12
251EEYu Zhong, Martin D. F. Wong: Fast Placement Optimization of Power Supply Pads. ASP-DAC 2007: 763-767
250EEYu Zhong, Martin D. F. Wong: Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid. ASP-DAC 2007: 768-773
249EELei Cheng, Deming Chen, Martin D. F. Wong: GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches. DAC 2007: 318-323
248EEHuaizhi Wu, Martin D. F. Wong: Improving Voltage Assignment by Outlier Detection and Incremental Placement. DAC 2007: 459-464
247EELei Cheng, Deming Chen, Martin D. F. Wong: DDBDD: Delay-Driven BDD Synthesis for FPGAs. DAC 2007: 910-915
246EELei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig: Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. ICCAD 2007: 370-375
245EEHui Kong, Tan Yan, Martin D. F. Wong, Muhammet Mustafa Ozdal: Optimal bus sequencing for escape routing in dense PCBs. ICCAD 2007: 390-395
244EETan Yan, Martin D. F. Wong: Untangling twisted nets for bus routing. ICCAD 2007: 396-400
243EEMuhammet Mustafa Ozdal, Martin D. F. Wong: Archer: a history-driven global routing algorithm. ICCAD 2007: 488-495
242EEHua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong: Is your layout density verification exact?: a fast exact algorithm for density calculation. ISPD 2007: 19-26
241EEHua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong: Dummy fill density analysis with coupling constraints. ISPD 2007: 3-10
240EEHua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong: OPC-Friendly Bus Driven Floorplanning. ISQED 2007: 847-852
239EEHuaizhi Wu, Martin D. F. Wong, I-Min Liu, Yusu Wang: Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1256-1269 (2007)
2006
238EESebastian Vogel, Martin D. F. Wong: Closed form solution for optimal buffer sizing using the Weierstrass elliptic function. ASP-DAC 2006: 315-319
237EELiang Deng, Martin D. F. Wong: An exact algorithm for the statistical shortest path problem. ASP-DAC 2006: 965-970
236EELei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. DAC 2006: 117-120
235EEHuaizhi Wu, Martin D. F. Wong, I-Min Liu: Timing-constrained and voltage-island-aware voltage assignment. DAC 2006: 429-432
234EEMuhammet Mustafa Ozdal, Martin D. F. Wong: Two-layer bus routing for high-speed printed circuit boards. ACM Trans. Design Autom. Electr. Syst. 11(1): 213-227 (2006)
233EEHung-Ming Chen, I-Min Liu, Martin D. F. Wong: I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2552-2556 (2006)
232EEMuhammet Mustafa Ozdal, Martin D. F. Wong: A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2784-2794 (2006)
231EELei Cheng, Martin D. F. Wong: Floorplan Design for Multimillion Gate FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2795-2805 (2006)
230EEMuhammet Mustafa Ozdal, Martin D. F. Wong: Algorithmic study of single-layer bus routing for high-speed boards. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 490-503 (2006)
229EEMuhammet Mustafa Ozdal, Martin D. F. Wong: Algorithms for simultaneous escape routing and Layer assignment of dense PCBs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1510-1522 (2006)
228EEXiaoping Tang, Ruiqi Tian, Martin D. F. Wong: Minimizing wire length in floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1744-1753 (2006)
227EEHua Xiang, Kai-Yuan Chao, Martin D. F. Wong: An ECO routing algorithm for eliminating coupling-capacitance violations. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1754-1762 (2006)
2005
226EELiang Deng, Martin D. F. Wong: Energy optimization in memory address bus structure for application-specific systems. ACM Great Lakes Symposium on VLSI 2005: 232-237
225EEGang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong: CMP aware shuttle mask floorplanning. ASP-DAC 2005: 1111-1114
224EEGang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong: Redundant-via enhanced maze routing for yield improvement. ASP-DAC 2005: 1148-1151
223EELei Cheng, Liang Deng, Martin D. F. Wong: Floorplanning for 3-D VLSI design. ASP-DAC 2005: 405-411
222EEXiaoping Tang, Ruiqi Tian, Martin D. F. Wong: Optimal redistribution of white space for wire length minimization. ASP-DAC 2005: 412-417
221EEYongseok Cheon, Martin D. F. Wong: Crowdedness-balanced multilevel partitioning for uniform resource utilization. ASP-DAC 2005: 418-423
220 Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wang: Post-placement voltage island generation under performance requirement. ICCAD 2005: 309-316
219 Liang Deng, Martin D. F. Wong: Buffer insertion under process variations for delay minimization. ICCAD 2005: 317-321
218 Yu Zhong, Martin D. F. Wong: Fast algorithms for IR drop analysis in large power grid. ICCAD 2005: 351-357
217 Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger: An escape routing framework for dense boards with high-speed design constraints. ICCAD 2005: 759-766
216 Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger: Optimal routing algorithms for pin clusters in high-density multichip modules. ICCAD 2005: 767-774
215EEHua Xiang, Kai-Yuan Chao, Martin D. F. Wong: Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. ISQED 2005: 181-186
214EEMuzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong: Current Calculation on VLSI Signal Interconnects. ISQED 2005: 580-585
213EEHua Xiang, I-Min Liu, Martin D. F. Wong: Wire Planning with Bounded Over-the-Block Wires. ISQED 2005: 622-627
212EEMuzhou Shao, Youxin Gao, Li-Pen Yuan, Martin D. F. Wong: IR Drop and Ground Bounce Awareness Timing Model. ISVLSI 2005: 226-231
211EEHua Xiang, Xiaoping Tang, Martin D. F. Wong: An algorithm for integrated pin assignment and buffer planning. ACM Trans. Design Autom. Electr. Syst. 10(3): 561-572 (2005)
210EEHung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong: Simultaneous power supply planning and noise avoidance in floorplan design. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 578-587 (2005)
2004
209EEXiaoping Tang, Martin D. F. Wong: On handling arbitrary rectilinear shape constraint. ASP-DAC 2004: 38-41
208EEXiaoping Tang, Martin D. F. Wong: Tradeoff routing resource, runtime and quality in buffered routing. ASP-DAC 2004: 430-433
207EELi-Da Huang, Martin D. F. Wong: Optical proximity correction (OPC): friendly maze routing. DAC 2004: 186-191
206EELiang Deng, Martin D. F. Wong: Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus. DATE 2004: 1104-1109
205EELei Cheng, Martin D. F. Wong: Floorplan design for multi-million gate FPGAs. ICCAD 2004: 292-299
204EEMuhammet Mustafa Ozdal, Martin D. F. Wong: Simultaneous escape routing and layer assignment for dense PCBs. ICCAD 2004: 822-829
203EEMuhammet Mustafa Ozdal, Martin D. F. Wong: A provably good algorithm for high performance bus routing. ICCAD 2004: 830-837
202EEMartin D. F. Wong: Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers. ICCD 2004: 106-110
201EEHung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang: I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. ICCD 2004: 562-567
200EEMuhammet Mustafa Ozdal, Martin D. F. Wong: A Two-Layer Bus Routing Algorithm for High-Speed Boards. ICCD 2004: 99-105
199EEEsra Erdem, Martin D. F. Wong: Rectilinear Steiner Tree Construction Using Answer Set Programming. ICLP 2004: 386-399
198EEHua Xiang, Kai-Yuan Chao, D. F. Wong: An ECO algorithm for eliminating crosstalk violations. ISPD 2004: 41-46
197EELi-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu: A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 141-147 (2004)
196EEHua Xiang, Xiaoping Tang, Martin D. F. Wong: Bus-driven floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 23(11): 1522-1530 (2004)
2003
195EEJohn F. Croix, D. F. Wong: Blade and razor: cell and interconnect delay analysis using current-based models. DAC 2003: 386-389
194EELi-Da Huang, Hung-Ming Chen, D. F. Wong: Global Wire Bus Configuration with Minimum Delay Uncertainty. DATE 2003: 10050-10055
193EESeokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun: Wire type assignment for FPGA routing. FPGA 2003: 61-67
192EESeokjin Lee, Yongseok Cheon, Martin D. F. Wong: A Min-Cost Flow Based Detailed Router for FPGAs. ICCAD 2003: 388-393
191EEMuhammet Mustafa Ozdal, Martin D. F. Wong: Length-Matching Routing for High-Speed Printed Circuit Boards. ICCAD 2003: 394-400
190EEHua Xiang, Xiaoping Tang, Martin D. F. Wong: Bus-Driven Floorplanning. ICCAD 2003: 66-73
189EEYongseok Cheon, Seokjin Lee, Martin D. F. Wong: Stable Multiway Circuit Partitioning for ECO. ICCAD 2003: 718-725
188EEMuzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee: Explicit gate delay model for timing evaluation. ISPD 2003: 32-38
187EEYao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong: Analysis of FPGA/FPIC switch modules. ACM Trans. Design Autom. Electr. Syst. 8(1): 11-37 (2003)
186EELi-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao: Maze routing with buffer insertion under transition time constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 91-95 (2003)
185EEYongseok Cheon, Martin D. F. Wong: Design hierarchy-guided multilevel circuit partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 420-427 (2003)
184EESeokjin Lee, Martin D. F. Wong: Timing-driven routing for FPGAs based on Lagrangian relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 506-510 (2003)
183EEHua Xiang, Xiaoping Tang, Martin D. F. Wong: Min-cost flow-based algorithm for simultaneous pin assignment and routing. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 870-878 (2003)
2002
182EEHua Xiang, D. F. Wong, Xiaoping Tang: An algorithm for integrated pin assignment and buffer planning. DAC 2002: 584-589
181EEXiaoping Tang, D. F. Wong: Floorplanning with alignment and performance constraints. DAC 2002: 848-853
180EELi-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu: A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. DATE 2002: 470-477
179EELi-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao: Maze Routing with Buffer Insertion under Transition Time Constraints. DATE 2002: 702-707
178EEK. K. Lee, D. F. Wong: Incremental reconfiguration of multi-FPGA systems. FPGA 2002: 206-213
177EEMuzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao: Shaping interconnect for uniform current density. ICCAD 2002: 254-259
176EERuiqi Tian, Ronggang Yu, Xiaoping Tang, D. F. Wong: On mask layout partitioning for electron projection lithography. ICCAD 2002: 514-518
175EEHua Xiang, Kai-Yuan Chao, D. F. Wong: ECO algorithms for removing overlaps between power rails and signal wires. ICCAD 2002: 67-74
174EESeokjin Lee, D. F. Wong: Timing-driven routing for FPGAs based on Lagrangian relaxation. ISPD 2002: 176-181
173EEYongseok Cheon, D. F. Wong: Design hierarchy guided multilevel circuit partitioning. ISPD 2002: 30-35
172EERuiqi Tian, Xiaoping Tang, Martin D. F. Wong: Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 63-71 (2002)
171EEMinghorng Lai, Martin D. F. Wong: Maze routing with buffer insertion and wiresizing. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1205-1209 (2002)
2001
170EEHung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang: Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ACM Great Lakes Symposium on VLSI 2001: 62-67
169EEMinghorng Lai, D. F. Wong: Memory-efficient interconnect optimization. ASP-DAC 2001: 198-202
168EEXiaoping Tang, D. F. Wong: FAST-SP: a fast algorithm for block placement based on sequence pair. ASP-DAC 2001: 521-526
167EEYouxin Gao, D. F. Wong: A fast and accurate delay estimation method for buffered interconnects. ASP-DAC 2001: 533-538
166EEI-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong: Integrated power supply planning and floorplanning. ASP-DAC 2001: 589-594
165EEMinghorng Lai, D. F. Wong: Slicing tree is a complete floorplan representation. DATE 2001: 228-232
164EEYouxin Gao, D. F. Wong: A graph based algorithm for optimal buffer insertion under accurate delay models. DATE 2001: 535-539
163EEK. K. Lee, D. F. Wong: LRoute: a delay minimal router for hierarchical CPLDs. FPGA 2001: 12-20
162EEHua Xiang, Xiaoping Tang, D. F. Wong: An Algorithm for Simultaneous Pin Assignment and Routing. ICCAD 2001: 232-
161EEXiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong: A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. ICCAD 2001: 49-56
160EERuiqi Tian, Xiaoping Tang, D. F. Wong: Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process. ISPD 2001: 118-123
159EEChris C. N. Chu, D. F. Wong: Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. ACM Trans. Design Autom. Electr. Syst. 6(3): 343-371 (2001)
158EEChris C. N. Chu, D. F. Wong: VLSI Circuit Performance Optimization by Geometric Programming. Annals OR 105(1-4): 37-60 (2001)
157EEXiaoping Tang, Ruiqi Tian, Martin D. F. Wong: Fast evaluation of sequence pair in block placement by longestcommon subsequence computation. IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1406-1413 (2001)
156EEYao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong: Matching-based algorithm for FPGA channel segmentation design. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 784-791 (2001)
155EEEvangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 800-807 (2001)
154EERuiqi Tian, Martin D. F. Wong, Robert Boone: Model-based dummy feature placement for oxide chemical-mechanicalpolishing manufacturability. IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 902-910 (2001)
153EEXiaoping Tang, D. F. Wong: Network flow based buffer planning. Integration 30(2): 143-155 (2001)
2000
152EEEsra Erdem, Vladimir Lifschitz, Martin D. F. Wong: Wire Routing and Satisfiability Planning. Computational Logic 2000: 822-836
151EEHai Zhou, D. F. Wong: Optimal low power X OR gate decomposition. DAC 2000: 104-107
150EEMinghorng Lai, D. F. Wong: Maze routing with buffer insertion and wiresizing. DAC 2000: 374-378
149EERuiqi Tian, D. F. Wong, Robert Boone: Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability. DAC 2000: 667-670
148EEXiaoping Tang, D. F. Wong, Ruiqi Tian: Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation. DATE 2000: 106-111
147EEI-Min Liu, Adnan Aziz, D. F. Wong: Meeting Delay Constraints in DSM by Minimal Repeater Insertion. DATE 2000: 436-440
146EEYouxin Gao, D. F. Wong: Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. DATE 2000: 512-
145EEXiaoping Tang, D. F. Wong: Planning buffer locations by network flows. ISPD 2000: 180-185
144EEI-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong: Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. ISPD 2000: 33-38
143EEYao-Wen Chang, Kai Zhu, D. F. Wong: Timing-driven routing for symmetrical array-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 5(3): 433-450 (2000)
142EEMartin D. F. Wong, Dwight D. Hill: Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 173-174 (2000)
141EEEvangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: Slicing floorplans with range constraint. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 272-278 (2000)
140EEHai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz: Simultaneous routing and buffer insertion with restrictions onbuffer locations. IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 819-824 (2000)
139EEWai-Kei Mak, D. F. Wong: A fast hypergraph min-cut algorithm for circuit partitioning. Integration 30(1): 1-11 (2000)
1999
138EEFung Yu Young, D. F. Wong: Slicing Floorplans with Boundary Constraint. ASP-DAC 1999: 17-20
137EEYouxin Gao, D. F. Wong: Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model. ASP-DAC 1999: 217-220
136EEChung-Ping Chen, D. F. Wong: Error Bounded Padé Approximation via Bilinear Conformal Transformation. DAC 1999: 7-12
135EEHai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz: Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. DAC 1999: 96-99
134EEHuiqun Liu, D. F. Wong: Circuit Partitioning for Dynamically Reconfigurable FPGAs. FPGA 1999: 187-194
133EEHung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani: Integrated floorplanning and interconnect planning. ICCAD 1999: 354-357
132EEHuiqun Liu, D. F. Wong: A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning. ICCAD 1999: 400-405
131EEJacob White, Jacob Avidan, Abe Elfadel, D. F. Wong: Advances in transistor timing, simulation, and optimization (tutorial abstract). ICCAD 1999: 611
130EEI-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou: An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. ICCD 1999: 210-215
129EEK. K. Lee, D. F. Wong: An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs. ICCD 1999: 216-221
128EEWai-Kei Mak, D. F. Wong: A fast hypergraph minimum cut algorithm. ISCAS (6) 1999: 170-173
127EEFung Yu Young, D. F. Wong: Slicing floorplans with range constraint. ISPD 1999: 97-102
126EEHai Zhou, Martin D. F. Wong: Global routing with crosstalk constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1683-1688 (1999)
125EEYouxin Gao, Martin D. F. Wong: Wire-sizing optimization with inductance consideration using transmission-line model. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1759-1767 (1999)
124EEChris C. N. Chu, Martin D. F. Wong: Greedy wire-sizing is linear time. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 398-405 (1999)
123EEChris C. N. Chu, Martin D. F. Wong: A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 787-798 (1999)
122EEChung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 1014-1025 (1999)
121EEYouxin Gao, Martin D. F. Wong: Optimal shape function for a bidirectional wire under Elmore delay model. IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 994-999 (1999)
120EEChris C. N. Chu, Martin D. F. Wong: An efficient and optimal algorithm for simultaneous buffer and wire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1297-1304 (1999)
119EEEvangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang: Slicing floorplans with boundary constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1385-1389 (1999)
118EEYouxin Gao, D. F. Wong: Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance. Integration 27(2): 165-178 (1999)
117EEFung Yu Young, Chris C. N. Chu, D. F. Wong: Generation of Universal Series-Parallel Boolean Functions. J. ACM 46(3): 416-435 (1999)
1998
116EEHai Zhou, D. F. Wong: Global Routing with Crosstalk Constraints. DAC 1998: 374-377
115EEMadhukar R. Korupolu, K. K. Lee, D. F. Wong: Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs. DAC 1998: 708-711
114EEChris C. N. Chu, D. F. Wong: A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. DATE 1998: 479-
113EEWai-Kei Mak, D. F. Wong: Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). FPGA 1998: 260
112EEHuiqun Liu, Kai Zhu, D. F. Wong: Circuit Partitioning with Complex Resource Constraints in FPGAs. FPGA 1998: 77-84
111EEFung Yu Young, D. F. Wong: Slicing floorplans with pre-placed modules. ICCAD 1998: 252-258
110EEYao-Wen Chang, Jai-Ming Lin, D. F. Wong: Graph matching-based algorithms for FPGA segmentation design. ICCAD 1998: 34-39
109EEHuiqun Liu, D. F. Wong: Network flow based circuit partitioning for time-multiplexed FPGAs. ICCAD 1998: 497-504
108EEYouxin Gao, D. F. Wong: Shaping a VLSI wire to minimize delay using transmission line model. ICCAD 1998: 611-616
107EEChung-Ping Chen, Chris C. N. Chu, D. F. Wong: Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. ICCAD 1998: 617-624
106EEChris C. N. Chu, D. F. Wong: Greedy wire-sizing is linear time. ISPD 1998: 39-44
105EEHai Zhou, D. F. Wong: Optimal river routing with crosstalk constraints. ACM Trans. Design Autom. Electr. Syst. 3(3): 496-514 (1998)
104EEHuiqun Liu, Martin D. F. Wong: Network-flow-based multiway partitioning with area and pin constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 50-59 (1998)
103EEChris C. N. Chu, Martin D. F. Wong: A matrix synthesis approach to thermal placement. IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1166-1174 (1998)
102EEHannah Honghua Yang, Martin D. F. Wong: Optimal min-area min-cut replication in partitioned circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1175-1183 (1998)
101EEKai Zhu, Martin D. F. Wong: Switch bound allocation for maximizing routability in timing-driven routing of FPGA's. IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 316-323 (1998)
1997
100EEJohn F. Croix, D. F. Wong: A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis. DAC 1997: 337-340
99EEChung-Ping Chen, D. F. Wong: Optimal Wire-Sizing Function with Fringing Capacitance Consideration. DAC 1997: 604-607
98EEHai Zhou, D. F. Wong: An exact gate decomposition algorithm for low-power technology mapping. ICCAD 1997: 575-580
97EEChris C. N. Chu, D. F. Wong: A new approach to simultaneous buffer insertion and wire sizing. ICCAD 1997: 614-621
96EEYouxin Gao, D. F. Wong: Optimal shape function for a bi-directional wire under Elmore delay model. ICCAD 1997: 622-627
95 Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi: Clustering and Load Balancing for Buffered Clock Tree Synthesis. ICCD 1997: 217-223
94 Fung Yu Young, D. F. Wong: On the Construction of Universal Series-Parallel Functions for Logic Module Design. ICCD 1997: 482-488
93 Wai-Kei Mak, D. F. Wong: Channel Segmentation Design for Symmentrical FPGAs. ICCD 1997: 496-501
92 Hai Zhou, D. F. Wong: Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation. ICCD 1997: 628-633
91EEHuiqun Liu, D. F. Wong: Network flow based multi-way partitioning with area and pin constraints. ISPD 1997: 12-17
90EEFung Yu Young, D. F. Wong: How good are slicing floorplans?. ISPD 1997: 144-149
89EEChris C. N. Chu, D. F. Wong: A matrix synthesis approach to thermal placement. ISPD 1997: 163-168
88EEChris C. N. Chu, D. F. Wong: Closed form solution to simultaneous buffer insertion/sizing and wire sizing. ISPD 1997: 192-197
87EEWai-Kei Mak, D. F. Wong: Board-level multiterminal net routing for FPGA-based logic emulation. ACM Trans. Design Autom. Electr. Syst. 2(2): 151-167 (1997)
86EEShashidhar Thakur, Yao-Wen Chang, Martin D. F. Wong, S. Muthukrishnan: Algorithms for an FPGA switch module routing problem with application to global routing. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 32-46 (1997)
85EEWai-Kei Mak, Martin D. F. Wong: Minimum replication min-cut partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1221-1227 (1997)
84EEWai-Kei Mak, Martin D. F. Wong: On optimal board-level routing for FPGA-based logic emulation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 282-289 (1997)
83EEKai Zhu, Martin D. F. Wong: Clock skew minimization during FPGA placement. IEEE Trans. on CAD of Integrated Circuits and Systems 16(4): 376-385 (1997)
82EET. W. Her, Martin D. F. Wong: Module implementation selection and its application to transistor placement. IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 645-651 (1997)
81EEHannah Honghua Yang, Martin D. F. Wong: Circuit clustering for delay minimization under area and pin constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 976-986 (1997)
80EEF. Y. Young, D. F. Wong: How good are slicing floorplans? Integration 23(1): 61-73 (1997)
79EEY. P. Chen, D. F. Wong: On retiming for FPGA logic module minimization. Integration 24(2): 135-145 (1997)
78EEY. P. Chen, D. F. Wong: A graph theoretic approach to feed-through pin assignment. Integration 24(2): 147-158 (1997)
1996
77EEShashidhar Thakur, D. F. Wong, Shankar Krishnamoorthy: Delay Minimal Decomposition of Multiplexers in Technology Mapping. DAC 1996: 254-257
76EEChung-Ping Chen, Yao-Wen Chang, D. F. Wong: Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. DAC 1996: 405-408
75EEChung-Ping Chen, Yao-Ping Chen, D. F. Wong: Optimal Wire-Sizing Formular Under the Elmore Delay Model. DAC 1996: 487-490
74EEShashidhar Thakur, D. F. Wong: Universal Logic Modules for Series-Parallel Functions. FPGA 1996: 31-37
73EEYao-Wen Chang, D. F. Wong, C. K. Wong: Universal Switch-Module Design for Symmetric-Array-Based FPGAs. FPGA 1996: 80-86
72EEWai-Kei Mak, D. F. Wong: Minimum replication min-cut partitioning. ICCAD 1996: 205-210
71EEHai Zhou, D. F. Wong: An optimal algorithm for river routing with crosstalk constraints. ICCAD 1996: 310-315
70EEChung-Ping Chen, Hai Zhou, D. F. Wong: Optimal non-uniform wire-sizing under the Elmore delay model. ICCAD 1996: 38-43
69EEYung-Ming Fang, D. F. Wong: Multiplexor Network Generation in High Level Synthesis. ICCD 1996: 78-
68EEShashidhar Thakur, D. F. Wong: Series-parallel functions and FPGA logic module design. ACM Trans. Design Autom. Electr. Syst. 1(1): 102-122 (1996)
67EEYao-Wen Chang, D. F. Wong, C. K. Wong: Universal switch modules for FPGA design. ACM Trans. Design Autom. Electr. Syst. 1(1): 80-101 (1996)
66EEHannah Honghua Yang, Martin D. F. Wong: Balanced partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1533-1540 (1996)
65EEGlenn G. Lai, Donald S. Fussell, Martin D. F. Wong: Hinted quad trees for VLSI geometry DRC based on efficient searching for neighbors. IEEE Trans. on CAD of Integrated Circuits and Systems 15(3): 317-324 (1996)
64EEMohankumar Guruswamy, Martin D. F. Wong: Echelon: a multilayer detailed area router. IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1126-1136 (1996)
1995
63EEWai-Kei Mak, D. F. Wong: On Optimal Board-Level Routing for FPGA-Based Logic Emulation. DAC 1995: 552-556
62EEShashidhar Thakur, D. F. Wong: On Designing ULM-based FPGA Logic Modules. FPGA 1995: 3-9
61EEHannah Honghua Yang, D. F. Wong: New algorithms for min-cut replication in partitioned circuits. ICCAD 1995: 216-222
60EEWai-Kei Mak, D. F. Wong: Board-level multi-terminal net routing for FPGA-based logic emulation. ICCAD 1995: 339-344
59EEKai-Yuan Chao, D. F. Wong: Signal integrity optimization on the pad assignment for high-speed VLSI design. ICCAD 1995: 720-725
58EEKai-Yuan Chao, D. F. Wong: Thermal placement for high-performance multichip modules. ICCD 1995: 218-223
57EEYao-Wen Chang, D. F. Wong, C. K. Wong: FPGA global routing based on a new congestion metric. ICCD 1995: 372-
56EEYao-Wen Chang, D. F. Wong, C. K. Wong: Design and analysis of FPGA/FPIC switch modules. ICCD 1995: 394-401
55EEShashidhar Thakur, D. F. Wong: Simultaneous area and delay minimum K-LUT mapping for K-exact networks. ICCD 1995: 402-408
54 Yao-Ping Chen, D. F. Wong: A Graph Theoretic Approach to Feed-Through Pin Assignment. ISCAS 1995: 1687-1690
53 Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong: An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. ISCAS 1995: 207-210
52 Kai-Yuan Chao, D. F. Wong: Floorplanning for Low Power Designs. ISCAS 1995: 45-48
51EERajmohan Rajaraman, Martin D. F. Wong: Optimum clustering for delay minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1490-1495 (1995)
50EETing-Chi Wang, Martin D. F. Wong, Yachyang Sun, Chak-Kuen Wong: Optimal net assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 265-269 (1995)
49EET. W. Her, Martin D. F. Wong: On over-the-cell channel routing with cell orientations consideration. IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 766-772 (1995)
48EET. W. Her, Ting-Chi Wang, Martin D. F. Wong: Performance-driven channel pin assignment algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 14(7): 849-857 (1995)
1994
47EEKai Zhu, D. F. Wong: Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs. DAC 1994: 165-170
46EEKai Zhu, D. F. Wong: Clock Skew Minimization During FPGA Placement. DAC 1994: 232-237
45EEShashidhar Thakur, D. F. Wong, S. Muthukrishnan: Algorithms for a switch module routing problem. EURO-DAC 1994: 265-270
44EEHannah Honghua Yang, D. F. Wong: Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. ICCAD 1994: 150-155
43EEYung-Ming Fang, D. F. Wong: Simultaneous functional-unit binding and floorplanning. ICCAD 1994: 317-321
42EEYao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong: A new global routing algorithm for FPGAs. ICCAD 1994: 356-361
41EEHonghua Yang, D. F. Wong: Efficient network flow based min-cut balanced partitioning. ICCAD 1994: 50-55
40EEKai-Yuan Chao, D. F. Wong: Layer assignment for high-performance multi-chip modules. ICCAD 1994: 680-685
39 Yao-Ping Chen, D. F. Wong: On Retiming for FPGA Logic Module Minimization. ICCD 1994: 394-397
38 T. W. Her, D. F. Wong: Over-the-Cell Routing with Cell Orientations Consideration. ISCAS 1994: 471-474
37EEYang Cai, Martin D. F. Wong: On shifting blocks and terminals to minimize channel density. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 178-186 (1994)
1993
36EERajmohan Rajaraman, D. F. Wong: Optimal Clustering for Delay Minimization. DAC 1993: 309-314
35EEGlenn G. Lai, Donald S. Fussell, D. F. Wong: HV/VH Trees: A New Spatial Data Structure for Fast Region Queries. DAC 1993: 43-47
34EEKai Zhu, D. F. Wong, Yao-Wen Chang: Switch module design with application to two-dimensional segmentation design. ICCAD 1993: 480-485
33 Yao-Ping Chen, Ting-Chi Wang, D. F. Wong: A Graph Partitioning Problem for Multiple-chip Design. ISCAS 1993: 1778-1781
32 Yao-Ping Chen, D. F. Wong: On optimal approximation of orthogonal polygons. ISCAS 1993: 2533-2536
31EEYang Cai, Martin D. F. Wong: Efficient via shifting algorithms in channel compaction. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1848-1857 (1993)
30EEYang Cai, Martin D. F. Wong: On minimizing the number of L-shaped channels in building-block layout [VLSI]. IEEE Trans. on CAD of Integrated Circuits and Systems 12(6): 757-769 (1993)
1992
29EETing-Chi Wang, D. F. Wong: A Graph Theoretic Technique to Speed up Floorplan Area Optimization. DAC 1992: 62-68
28EEKai Zhu, D. F. Wong: On channel segmentation design for row-based FPGAs. ICCAD 1992: 26-29
27 Yang Cai, D. F. Wong: Channel Density Minimization by Pin Permutation. ICCD 1992: 378-382
26EEShinichiro Haruyama, Martin D. F. Wong, Donald S. Fussell: Topological channel routing [VLSI]. IEEE Trans. on CAD of Integrated Circuits and Systems 11(10): 1177-1197 (1992)
25EETing-Chi Wang, Martin D. F. Wong: Optimal floorplan area optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 992-1002 (1992)
1991
24EEYang Cai, D. F. Wong: On Minimizing the Number of L-Shaped Channels. DAC 1991: 328-334
23EEMohankumar Guruswamy, D. F. Wong: A General Multi-Layer Area Router. DAC 1991: 335-340
22 Yang Cai, D. F. Wong: Minimizing Channel Density by Shifting Blocks and Terminals. ICCAD 1991: 524-527
21 T. W. Her, D. F. Wong: Optimal Module Implementation and Its Application to Transistor Placement. ICCAD 1991: 98-101
20 John C. Chan, Baxter F. Womack, D. F. Wong: On the Manisfestation of Faults to Errors in Signature Analysis. ICCD 1991: 360-363
19 Khe-Sing The, D. F. Wong: Area Optimization for Higher Order Hierarchical Floorplans. ICCD 1991: 520-523
18 D. F. Wong, Edward M. Reingold: Probabilistic Analysis of a Grouping Algorithm. Algorithmica 6(2): 192-206 (1991)
17EEYang Cai, Martin D. F. Wong: Optimal channel pin assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 10(11): 1413-1424 (1991)
16EEMartin D. F. Wong, Mohankumar Guruswamy: Channel ordering for VLSI layout with rectilinear modules. IEEE Trans. on CAD of Integrated Circuits and Systems 10(11): 1425-1431 (1991)
15EEYang Cai, Martin D. F. Wong: Channel/switchbox definition for VLSI building-block layout. IEEE Trans. on CAD of Integrated Circuits and Systems 10(12): 1485-1493 (1991)
14EEKhe-Sing The, Martin D. F. Wong, Jason Cong: A layout modification approach to via minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 536-541 (1991)
1990
13EETing-Chi Wang, D. F. Wong: An Optimal Algorithm for Floorplan Area Optimization. DAC 1990: 180-186
12EEYang Cai, D. F. Wong: A Channel/Switchbox Definition Algorithm for Building-Block Layout. DAC 1990: 638-641
11EEYang Cai, D. F. Wong: Optimal via-shifting in channel compaction. EURO-DAC 1990: 186-190
10 Yang Cai, D. F. Wong: An Optimal Channel Pin Assignment Algorithm. ICCAD 1990: 10-13
9 T. W. Her, D. F. Wong, T. H. Freeman: Optimal Orientations of Transistor Chains. ICCAD 1990: 524-527
8 Shinichiro Haruyama, D. F. Wong, Donald S. Fussell: Topological Routing Using Geometric Information. ICCAD 1990: 6-9
1989
7EED. F. Wong, P. S. Sakhamuri: Efficient Floorplan Area Optimization. DAC 1989: 586-589
6EEKhe-Sing The, D. F. Wong, Jason Cong: VIA Minimization by Layout Modification. DAC 1989: 799-802
5 D. F. Wong, C. L. Liu: Floorplan Design of VLSI Circuits. Algorithmica 4(2): 263-291 (1989)
1988
4EEJingsheng Cong, D. F. Wong: How to Obtain More Compactable Channel Routing Solutions. DAC 1988: 663-666
3EEJason Cong, Martin D. F. Wong, C. L. Liu: A new approach to three- or four-layer channel routing. IEEE Trans. on CAD of Integrated Circuits and Systems 7(10): 1094-1104 (1988)
1987
2EED. F. Wong, C. L. Liu: Array Optimization for VLSI Synthesis. DAC 1987: 537-543
1986
1EED. F. Wong, C. L. Liu: A new algorithm for floorplan design. DAC 1986: 101-107

Coauthor Index

1Jacob Avidan [131]
2Adnan Aziz [130] [135] [140] [144] [147] [166]
3Robert Boone [149] [154]
4Yang Cai [10] [11] [12] [15] [17] [22] [24] [27] [30] [31] [37]
5Huijing Cao [177] [188]
6John C. Chan [20]
7Yao-Wen Chang [34] [42] [56] [57] [67] [73] [76] [86] [110] [143] [156] [187] [269] [270]
8Kai-Yuan Chao [40] [52] [53] [58] [59] [175] [198] [215] [227] [241] [242] [253] [255] [256]
9Charlie Chung-Ping Chen (Chung-Ping Chen) [70] [75] [76] [99] [107] [122] [136]
10Deming Chen [236] [246] [247] [249] [254] [260] [264]
11Hung-Ming Chen [133] [166] [170] [194] [201] [210] [214] [233]
12Y. P. Chen [78] [79]
13Yao-Ping Chen [32] [33] [39] [54] [75] [95]
14Lei Cheng [205] [223] [231] [236] [246] [247] [249] [254] [260]
15Yongseok Cheon [173] [185] [189] [192] [221]
16Tan-Li Chou [144] [166]
17Chris C. N. Chu (Chris Chu, Chris Chong-Nuen Chu) [88] [89] [97] [103] [106] [107] [114] [117] [120] [122] [123] [124] [158] [159]
18Jason Cong [3] [6] [14]
19Jingsheng Cong [4]
20John F. Croix [100] [195]
21Liang Deng [206] [219] [223] [226] [236] [237] [240] [241] [252] [253] [255]
22Quang Dinh [264]
23Abe Elfadel [131]
24Esra Erdem [152] [199]
25Jia-Wei Fang [270]
26Yung-Ming Fang [43] [69]
27T. H. Freeman [9]
28Donald S. Fussell [8] [26] [35] [65]
29Youxin Gao [96] [108] [118] [121] [125] [137] [146] [164] [167] [177] [179] [186] [188] [212] [214]
30Wilsin Gosti [259]
31Jason Govig [246]
32Mohankumar Guruswamy [16] [23] [64]
33Shinichiro Haruyama [8] [26]
34T. W. Her [9] [21] [38] [48] [49] [82]
35Dwight D. Hill [142]
36Philip S. Honsinger [216] [217] [257] [258]
37Li-Da Huang [179] [180] [186] [188] [194] [197] [201] [207] [210] [224] [240]
38Michael Hutton (Michael D. Hutton, Mike Hutton) [246]
39Hui Kong [245] [272]
40Madhukar R. Korupolu [115]
41Shankar Krishnamoorthy [77]
42Glenn G. Lai [35] [65]
43Minghorng Lai [150] [165] [169] [171] [179] [186]
44K. K. Lee [115] [129] [163] [178]
45Seokjin Lee [174] [184] [188] [189] [192] [193]
46Vladimir Lifschitz [152]
47Jai-Ming Lin [110] [156]
48Po-Hung Lin [269]
49C. L. Liu (Chung Laung (Dave) Liu) [1] [2] [3] [5]
50Huiqun Liu [91] [104] [109] [112] [132] [134]
51I-Min Liu [130] [135] [140] [144] [147] [166] [180] [197] [201] [210] [213] [220] [233] [235] [239]
52Lijuan Luo [265] [273]
53Wai-Kei Mak [60] [63] [72] [84] [85] [87] [93] [113] [128] [139] [170]
54Ashih D. Mehta [95]
55Noel Menezes [95]
56S. Muthukrishnan (S. Muthu Muthukrishnan) [45] [86]
57Muhammet Mustafa Ozdal [191] [200] [203] [204] [216] [217] [229] [230] [232] [234] [243] [245] [257] [258] [266]
58David Z. Pan (David Zhigang Pan) [224] [225]
59David M. Pawlowski [252]
60Lawrence T. Pileggi (Larry T. Pileggi, Lawrence T. Pillage) [95]
61Ruchir Puri [241] [242] [255] [256]
62Rajmohan Rajaraman [36] [51]
63Edward M. Reingold [18]
64P. S. Sakhamuri [7]
65Muzhou Shao [177] [188] [201] [212] [214]
66Naveed A. Sherwani [133]
67Richard Y. Sun [193]
68Yachyang Sun [50]
69Xiaoping Tang [145] [148] [153] [157] [160] [161] [162] [168] [172] [176] [180] [181] [182] [183] [190] [196] [197] [208] [209] [211] [222] [228]
70Shashidhar Thakur [42] [45] [53] [55] [62] [68] [74] [77] [86]
71Khe-Sing The [6] [14] [19]
72Ruiqi Tian [148] [149] [154] [157] [160] [161] [172] [176] [222] [225] [228]
73Sebastian Vogel [238]
74Ting-Chi Wang [13] [25] [29] [33] [48] [50]
75Yusu Wang [220] [239]
76Jacob K. White (Jacob White) [131]
77Baxter F. Womack [20]
78Chak-Kuen Wong (C. K. Wong) [50] [56] [57] [67] [73] [187]
79Guang-Ming Wu [187]
80Huaizhi Wu [220] [235] [239] [248] [259] [267]
81Hua Xiang [161] [162] [175] [180] [182] [183] [190] [193] [196] [197] [198] [211] [213] [215] [227] [240] [241] [242] [253] [255] [256]
82Gang Xu [224] [225]
83Tan Yan [244] [245] [263] [268] [271] [272]
84Hannah Honghua Yang (Honghua Yang) [41] [44] [61] [66] [81] [102] [119] [133] [141] [155] [170] [261]
85Evangeline F. Y. Young (F. Y. Young, Fung Yu Young) [80] [90] [94] [111] [117] [119] [127] [133] [138] [141] [155]
86Ronggang Yu [176]
87Li-Pen Yuan [177] [188] [212] [214]
88Hongbo Zhang [269]
89Yu Zhong [218] [250] [251] [262]
90Hai Zhou [70] [71] [92] [98] [105] [116] [126] [130] [133] [135] [140] [151]
91Kai Zhu [28] [34] [42] [46] [47] [83] [101] [112] [143] [187]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)