| * | 2009 |
|---|
| 9 | EE | Nishant Patil,
Albert Lin,
Jie Zhang,
H.-S. Philip Wong,
Subhasish Mitra:
Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.
DAC 2009: 304-309 |
| 2008 |
|---|
| 8 | EE | Nishant Patil,
Jie Deng,
Albert Lin,
H.-S. Philip Wong,
Subhasish Mitra:
Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1725-1736 (2008) |
| 7 | EE | Jie Deng,
Albert Lin,
Gordon C. Wan,
H.-S. Philip Wong:
Carbon nanotube transistor compact model for circuit design and performance optimization.
JETC 4(2): (2008) |
| 2007 |
|---|
| 6 | EE | Nishant Patil,
Jie Deng,
H.-S. Philip Wong,
Subhasish Mitra:
Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits.
DAC 2007: 958-961 |
| 5 | EE | Jie Deng,
Keunwoo Kim,
Ching-Te Chuang,
H.-S. Philip Wong:
Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI.
ISQED 2007: 145-152 |
| 2006 |
|---|
| 4 | EE | H.-S. Philip Wong,
Jie Deng,
Arash Hazeghi,
Tejas Krishnamohan,
Gordon C. Wan:
Carbon nanotube transistor circuits: models and tools for design and performance optimization.
ICCAD 2006: 651-654 |
| 3 | EE | H.-S. Philip Wong:
Device and Technology Challenges for Nanoscale CMOS.
ISQED 2006: 515-518 |
| 2002 |
|---|
| 2 | EE | H.-S. Philip Wong:
Beyond the conventional transistor.
IBM Journal of Research and Development 46(2-3): 133-168 (2002) |
| 1995 |
|---|
| 1 | | Yuan Taur,
Yuh-Jier Mii,
David J. Frank,
H.-S. Philip Wong,
Douglas A. Buchanan,
Shalom J. Wind,
Stephen A. Rishton,
Watson A. Sai-Halasz,
Edward J. Nowak:
CMOS scaling into the 21st century: 0.1 µm and beyond.
IBM Journal of Research and Development 39(1-2): 245-260 (1995) |
