Zhongfeng Wang

2008
20	EE	Zhiqiang Cui, Zhongfeng Wang: Extended layered decoding of LDPC codes. ACM Great Lakes Symposium on VLSI 2008: 457-462
2007
19	EE	Jun Ma, Alexander Vardy, Zhongfeng Wang, Qinqin Chen: Direct Root Computation Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. ISCAS 2007: 1409-1412
18	EE	Qinqin Chen, Zhongfeng Wang, Jun Ma: FPGA Implementation of an Interpolation Processor for Soft-Decision Decoding of Reed-Solomon Codes. ISCAS 2007: 2100-2103
17	EE	Zhiqiang Cui, Zhongfeng Wang: Efficient Message Passing Architecture for High Throughput LDPC Decoder. ISCAS 2007: 917-920
16	EE	Zhongfeng Wang, Zhiqiang Cui: Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. IEEE Trans. VLSI Syst. 15(1): 104-114 (2007)
15	EE	Jun Ma, Alexander Vardy, Zhongfeng Wang: Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. VLSI Syst. 15(11): 1225-1238 (2007)
14	EE	Zhongfeng Wang, Zhiqiang Cui: A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. IEEE Trans. VLSI Syst. 15(4): 483-488 (2007)
2006
13	EE	Jin Sha, Ming-Lun Gao, Zhongjin Zhang, Li Li, Zhongfeng Wang: An FPGA Implementation of Array LDPC Decoder. APCCAS 2006: 1675-1678
12	EE	Zhiqiang Cui, Zhongfeng Wang: A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA. ISCAS 2006
11	EE	Zhiqiang Cui, Zhongfeng Wang: Area-efficient parallel decoder architecture for high rate QC-LDPC codes. ISCAS 2006
10	EE	Jun Ma, Alexander Vardy, Zhongfeng Wang: Efficient fast interpolation architecture for soft-decision decoding of Reed-Solomon codes. ISCAS 2006
9	EE	Qingwei Li, Zhongfeng Wang: Improved k-best sphere decoding algorithms for MIMO systems. ISCAS 2006
8	EE	Jun Ma, Alexander Vardy, Zhongfeng Wang: Reencoder design for soft-decision decoding of an (255, 239) Reed-Solomon code. ISCAS 2006
7	EE	Zhongfeng Wang, Jun Ma: High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. VLSI Syst. 14(9): 937-950 (2006)
2005
6	EE	Zhongfeng Wang, Qing-wei Jia: Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes. ISCAS (6) 2005: 5786-5789
2004
5	EE	Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi: On the better protection of short-frame turbo codes. IEEE Transactions on Communications 52(9): 1435-1439 (2004)
2003
4	EE	Zhongfeng Wang, Yiyan Tang, Yuke Wang: Low hardware complexity parallel turbo decoder architecture. ISCAS (2) 2003: 53-56
2002
3	EE	Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi: Area-efficient high-speed decoding schemes for turbo decoders. IEEE Trans. VLSI Syst. 10(6): 902-912 (2002)
2001
2	EE	Tong Zhang, Zhongfeng Wang, Keshab K. Parhi: On finite precision implementation of low density parity check codes decoder. ISCAS (4) 2001: 202-205
1999
1	EE	S. Summerfield, Zhongfeng Wang, Keshab K. Parhi: Area-power-time efficient pipeline-interleaved architectures for wave digital filters. ISCAS (3) 1999: 343-346

Coauthor Index

1	Qinqin Chen	[18] [19]
2	Zhipei Chi	[3] [5]
3	Zhiqiang Cui	[11] [12] [14] [16] [17] [20]
4	Ming-Lun Gao	[13]
5	Qing-wei Jia	[6]
6	Li Li	[13]
7	Qingwei Li	[9]
8	Jun Ma	[7] [8] [10] [15] [18] [19]
9	Keshab K. Parhi	[1] [2] [3] [5]
10	Jin Sha	[13]
11	S. Summerfield	[1]
12	Yiyan Tang	[4]
13	Alexander Vardy	[8] [10] [15] [19]
14	Yuke Wang	[4]
15	Tong Zhang	[2]
16	Zhongjin Zhang	[13]

Colors in the list of coauthors