| 2008 |
|---|
| 24 | EE | Fang Gong,
Wenjian Yu,
Zeyi Wang,
Zhiping Yu,
Changhao Yan:
Efficient techniques for 3-D impedance extraction using mixed boundary element method.
ASP-DAC 2008: 158-163 |
| 2007 |
|---|
| 23 | EE | Xiren Wang,
Wenjian Yu,
Zeyi Wang:
A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy Substrates.
ASP-DAC 2007: 62-67 |
| 2006 |
|---|
| 22 | EE | Mengsheng Zhang,
Wenjian Yu,
Yu Du,
Zeyi Wang:
An efficient algorithm for 3-D reluctance extraction considering high frequency effect.
ASP-DAC 2006: 521-526 |
| 21 | EE | Xiren Wang,
Wenjian Yu,
Zeyi Wang:
A new boundary element method for accurate modeling of lossy substrates with arbitrary doping profiles.
ASP-DAC 2006: 683-688 |
| 20 | EE | Changhao Yan,
Wenjian Yu,
Zeyi Wang:
Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method.
ASP-DAC 2006: 844-849 |
| 19 | EE | Changhao Yan,
Wenjian Yu,
Zeyi Wang:
A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects.
ISQED 2006: 709-716 |
| 18 | EE | Wenjian Yu,
Mengsheng Zhang,
Zeyi Wang:
Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 12-18 (2006) |
| 17 | EE | Xiren Wang,
Wenjian Yu,
Zeyi Wang:
Efficient Direct Boundary Element Method for Resistance Extraction of Substrate With Arbitrary Doping Profile.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 3035-3042 (2006) |
| 2005 |
|---|
| 16 | EE | Xiren Wang,
Wenjian Yu,
Zeyi Wang,
Xianlong Hong:
An improved direct boundary element method for substrate coupling resistance extraction.
ACM Great Lakes Symposium on VLSI 2005: 84-87 |
| 15 | EE | Xiren Wang,
Wenjian Yu,
Zeyi Wang:
Substrate resistance extraction with direct boundary element method.
ASP-DAC 2005: 208-211 |
| 14 | EE | Xiren Wang,
Deyan Liu,
Wenjian Yu,
Zeyi Wang:
Improved Boundary Element Method for Fast 3-D Interconnect Resistance Extraction.
IEICE Transactions 88-C(2): 232-240 (2005) |
| 2004 |
|---|
| 13 | EE | Liu Yang,
Xiaobo Guo,
Zeyi Wang:
An efficient method MEGCR for solving systems with multiple right-hand sides in 3-D parasitic inductance extraction.
ASP-DAC 2004: 702-706 |
| 12 | EE | Xiren Wang,
Deyan Liu,
Wenjian Yu,
Zeyi Wang:
Fast and accurate extraction of 3-D interconnect resistance: improved quasi-multiple medium accelerated BEM method.
ASP-DAC 2004: 707-709 |
| 11 | EE | Zhaozhi Yang,
Zeyi Wang:
New Multipole Method for 3-D Capacitance Extraction.
J. Comput. Sci. Technol. 19(4): 544- (2004) |
| 2003 |
|---|
| 10 | EE | Wenjian Yu,
Zeyi Wang,
Xianlong Hong:
Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics.
ICCD 2003: 58-63 |
| 2002 |
|---|
| 9 | EE | Shuzhou Fang,
Zeyi Wang,
Xianlong Hong:
A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI.
ASP-DAC 2002: 305-310 |
| 8 | EE | Shuzhou Fang,
Zeyi Wang,
Xianlong Hong:
A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI.
VLSI Design 2002: 305-310 |
| 2001 |
|---|
| 7 | EE | Zhaozhi Yang,
Zeyi Wang,
Shuzhou Fang:
A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance.
ASP-DAC 2001: 214-218 |
| 6 | EE | Wenjian Yu,
Zeyi Wang:
An efficient quasi-multiple medium algorithm fo the capacitance extraction of actual 3-D VLSI interconnects.
ASP-DAC 2001: 366-372 |
| 2000 |
|---|
| 5 | EE | Jiangchun Gu,
Zeyi Wang,
Xianlong Hong:
Hierarchical computation of 3-D interconnect capacitance using direct boundary element method.
ASP-DAC 2000: 447-452 |
| 4 | EE | Shuzhou Fang,
Xiaobo Tang,
Zeyi Wang,
Xianlong Hong:
A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section.
ASP-DAC 2000: 453-456 |
| 1999 |
|---|
| 3 | EE | Jinsong Hou,
Zeyi Wang,
Xianlong Hong:
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance.
ASP-DAC 1999: 93- |
| 1996 |
|---|
| 2 | EE | Zeyi Wang,
Yanhong Yuan,
Qiming Wu:
A parallel multipole accelerated 3-D capacitance simulator based on an improved model.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1441-1450 (1996) |
| 1992 |
|---|
| 1 | EE | Zeyi Wang,
Qiming Wu:
A two-dimensional resistance simulator using the boundary element method.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(4): 497-504 (1992) |
