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Chih-Wea Wang Vis

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*2007
14EEChih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu: STEAC: A Platform for Automatic SOC Test Integration. IEEE Trans. VLSI Syst. 15(5): 541-545 (2007)
2004
13EEYu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu: Failure Factor Based Yield Enhancement for SRAM Designs. DFT 2004: 20-28
12EEKuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee: An SOC Test Integration Platform and Its Industrial Realization. ITC 2004: 1213-1222
2003
11EEKuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu: FAME: A Fault-Pattern Based Memory Failure Analysis Framework. ICCAD 2003: 595-598
10EEChih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang: Fault Pattern Oriented Defect Diagnosis for Memories. ITC 2003: 29-38
9EEChih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu: Test and Diagnosis of Word-Oriented Multiport Memories. VTS 2003: 248-253
2002
8EEChih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin: Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium 2002: 356-
7EEHuan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin: Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium 2002: 411-
6EEKuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu: RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. VTS 2002: 281-288
5EEChih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin: A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM. J. Electronic Testing 18(6): 637-647 (2002)
2001
4EEChih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang: A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. Asian Test Symposium 2001: 103-
3EEChi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu: Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. DAC 2001: 301-306
2000
2EEChih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin: A built-in self-test and self-diagnosis scheme for embedded SRAM. Asian Test Symposium 2000: 45-50
1 Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu: Error Catch and Analysis for Semiconductor Memories Using March Tests. ICCAD 2000: 468-471

Coauthor Index

1Kuo-Liang Cheng [1] [3] [6] [7] [8] [9] [10] [11] [12] [14]
2Kevin Chiu [2] [5]
3Yung-Fa Chou [10] [11]
4Li-Ming Denq [12]
5Yu-Tsao Hsing [13]
6Huan-Shan Hsu [7]
7Chih-Tsun Huang [1] [3] [4] [6] [7] [8] [9] [10] [11] [12] [13]
8Frank Huang [10]
9Jing-Reng Huang [7] [8] [12] [14]
10Shi-Yu Huang [4]
11Shin-Wei Hung [12]
12Jih-Nung Lee [10] [11]
13Jye-Yuan Lee [12]
14Jin-Fu Li [2] [5]
15Hsiao-Ping Lin [2] [5]
16Shyh-Horng Lin [4]
17Yen-Fu Lin [8]
18Youn-Long Lin [7] [8]
19Chih-Yen Lo [12] [14]
20Tony Teng [2] [5]
21Ruey-Shing Tzeng [4]
22Chen-Hsing Wang [14]
23Hsin-Po Wang [4]
24Shin-Moe Wang [14]
25Cheng-Wen Wu [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14]
26Chi-Feng Wu [1] [2] [3] [4] [5]
27Ching-Wei Wu [13]
28Hong-Tzer Yang [10]
29Jen-Chieh Yeh [6]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)