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* | 2009 | |
---|---|---|

94 | EE | Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula: A scalable parallel H.264 decoder on the cell broadband engine architecture. CODES+ISSS 2009: 353-362 |

93 | EE | Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha: Throughput optimal task allocation under thermal constraints for multi-core processors. DAC 2009: 776-781 |

92 | EE | Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha: Performance optimal speed control of multi-core processors under thermal constraints. DATE 2009: 1548-1551 |

2008 | ||

91 | EE | Tejaswi Gowda, Sarma B. K. Vrudhula: Decomposition based approach for synthesis of multi-level threshold logic circuits. ASP-DAC 2008: 125-130 |

90 | Tejaswi Gowda, Samuel Leshner, Sarma B. K. Vrudhula, Seungchan Kim: Threshold Logic Gene Regulatory Model - Prediction of Dorsal-ventral Patterning and Hardware-based Simulation of Drosophila. BIODEVICES (1) 2008: 212-219 | |

89 | EE | Amit Goel, Sarma B. K. Vrudhula: Statistical waveform and current source based standard cell models for accurate timing analysis. DAC 2008: 227-230 |

88 | EE | Amit Goel, Sarma B. K. Vrudhula: Current source based standard cell model for accurate signal integrity and timing analysis. DATE 2008: 574-579 |

87 | EE | Ravishankar Rao, Sarma B. K. Vrudhula: Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors. ICCAD 2008: 537-542 |

86 | EE | Ravishankar Rao, Sarma B. K. Vrudhula, Krzysztof S. Berezowski: Analytical results for design space exploration of multi-core processors employing thread migration. ISLPED 2008: 229-232 |

85 | EE | Saravanan Ramamoorthy, Haibo Wang, Sarma B. K. Vrudhula: A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design. ISQED 2008: 123-126 |

84 | EE | Amit Goel, Sarma B. K. Vrudhula, Feroze Taraporevala, Praveen Ghanta: A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations. ISQED 2008: 200-206 |

83 | EE | Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Temperature and Process Variations Aware Power Gating of Functional Units. VLSI Design 2008: 515-520 |

82 | EE | Kyungsoo Lee, Naehyuck Chang, Jianli Zhuo, Chaitali Chakrabarti, Sudheendra Kadri, Sarma B. K. Vrudhula: A fuel-cell-battery hybrid for portable embedded systems. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |

81 | EE | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel: A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1812-1825 (2008) |

80 | EE | Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 445-455 (2008) |

2007 | ||

79 | EE | Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevod: Combinational equivalence checking for threshold logic circuits. ACM Great Lakes Symposium on VLSI 2007: 102-107 |

78 | EE | Ravishankar Rao, Sarma B. K. Vrudhula: Performance optimal processor throttling under thermal constraints. CASES 2007: 257-266 |

77 | EE | Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao: The Impact of NBTI on the Performance of Combinational and Sequential Circuits. DAC 2007: 364-369 |

76 | EE | Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti: Throughput of multi-core processors under thermal constraints. ISLPED 2007: 201-206 |

75 | EE | Krzysztof S. Berezowski, Sarma B. K. Vrudhula: Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. ISMVL 2007: 24 |

74 | EE | Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula: Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. PATMOS 2007: 125-137 |

73 | EE | Sarvesh Bhardwaj, Sarma B. K. Vrudhula: A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. VLSI Design 2007: 589-594 |

72 | EE | Sarma B. K. Vrudhula, Sarvesh Bhardwaj: Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. VLSI Design 2007: 9 |

71 | EE | Ravishankar Rao, Sarma B. K. Vrudhula: Energy optimal speed control of a producer--consumer device pair. ACM Trans. Embedded Comput. Syst. 6(4): (2007) |

70 | EE | Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang: Stochastic Power Grid Analysis Considering Process Variations CoRR abs/0710.4649: (2007) |

69 | EE | Praveen Ghanta, Sarma B. K. Vrudhula: Analysis of Power Supply Noise in the Presence of Process Variations. IEEE Design & Test of Computers 24(3): 256-266 (2007) |

2006 | ||

68 | EE | Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula: Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. ASP-DAC 2006: 953-958 |

67 | EE | Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda: Stochastic variational analysis of large power grids considering intra-die correlations. DAC 2006: 211-216 |

66 | EE | Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula: Extending the lifetime of fuel cell based hybrid systems. DAC 2006: 562-567 |

65 | EE | Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti, Sarma B. K. Vrudhula: High-level power management of embedded systems with application-specific energy cost functions. DAC 2006: 568-573 |

64 | EE | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao: Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. DAC 2006: 791-796 |

63 | EE | Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula: A framework for statistical timing analysis using non-linear delay and slew models. ICCAD 2006: 225-230 |

62 | EE | Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti, Naehyuck Chang: An optimal analytical solution for processor speed control with thermal constraints. ISLPED 2006: 292-297 |

61 | EE | Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula: Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids. ISLPED 2006: 424-429 |

60 | EE | Praveen Ghanta, Sarma B. K. Vrudhula: Variational Interconnect Delay Metrics for Statistical Timing Analysis. ISQED 2006: 19-24 |

59 | EE | Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula: LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. ISQED 2006: 717-722 |

58 | EE | Sarma B. K. Vrudhula, Janet Meiling Wang, Praveen Ghanta: Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2001-2011 (2006) |

57 | EE | Ravishankar Rao, Sarma B. K. Vrudhula: Energy-Optimal Speed Control of a Generic Device. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2737-2746 (2006) |

56 | EE | Kaviraj Chopra, Sarma B. K. Vrudhula: Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2820-2832 (2006) |

55 | EE | Tao Shu, Marwan Krunz, Sarma B. K. Vrudhula: Joint Optimization of Transmit Power-Time and Bit Energy Efficiency in CDMA Wireless Sensor Networks. IEEE Transactions on Wireless Communications 5(11): 3109-3118 (2006) |

54 | EE | Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula: Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. J. Low Power Electronics 2(2): 240-250 (2006) |

2005 | ||

53 | EE | Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Leakage minimization of nano-scale circuits in the presence of systematic and random variations. DAC 2005: 541-546 |

52 | EE | Ravishankar Rao, Sarma B. K. Vrudhula: Energy optimal speed control of devices with discrete speed sets. DAC 2005: 901-904 |

51 | EE | Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang: Stochastic Power Grid Analysis Considering Process Variations. DATE 2005: 964-969 |

50 | EE | Krzysztof S. Berezowski, Sarma B. K. Vrudhula: Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. DSD 2005: 139-143 |

49 | Ravishankar Rao, Sarma B. K. Vrudhula: Battery optimization vs energy optimization: which to choose and when? ICCAD 2005: 439-445 | |

48 | Sarvesh Bhardwaj, Sarma B. K. Vrudhula: Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. ICCAD 2005: 713-718 | |

47 | EE | Tao Shu, Marwan Krunz, Sarma B. K. Vrudhula: Power balanced coverage-time optimization for clustered wireless sensor networks. MobiHoc 2005: 111-120 |

46 | EE | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Probability distribution of signal arrival times using Bayesian networks. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1784-1794 (2005) |

2004 | ||

45 | EE | Ravishankar Rao, Sarma B. K. Vrudhula, Musaravakkam S. Krishnan: Disk drive energy optimization for audio-video applications. CASES 2004: 93-103 |

44 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula: Variational delay metrics for interconnect timing analysis. DAC 2004: 381-384 |

43 | EE | Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang: A methodology to improve timing yield in the presence of process variations. DAC 2004: 448-453 |

42 | EE | Kaviraj Chopra, Sarma B. K. Vrudhula: Implicit pseudo boolean enumeration algorithms for input vector control. DAC 2004: 767-772 |

41 | EE | Sridhar Dasika, Sarma B. K. Vrudhula, Kaviraj Chopra, R. Srinivasan: A Framework for Battery-Aware Sensor Management. DATE 2004: 962-967 |

40 | EE | Ravishankar Rao, Sarma B. K. Vrudhula: Energy optimization for a two-device data flow chain. ICCAD 2004: 268-274 |

39 | EE | Janet Meiling Wang, Praveen Ghanta, Sarma B. K. Vrudhula: Stochastic analysis of interconnect performance in the presence of process variations. ICCAD 2004: 880-886 |

38 | EE | Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj: Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. VLSI Design 2004: 240- |

37 | EE | Raghukiran Sreeramaneni, Sarma B. K. Vrudhula: Energy Profiler for Hardware/Software Co-Design. VLSI Design 2004: 335- |

2003 | ||

36 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Computation and Refinement of Statistical Bounds on Circuit Delay. DAC 2003: 348-353 |

35 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical Timing Analysis Using Bounds. DATE 2003: 10062-10067 |

34 | EE | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: AU: Timing Analysis Under Uncertainty. ICCAD 2003: 615-620 |

33 | EE | Ravishankar Rao, Sarma B. K. Vrudhula, Daler N. Rakhmatov: Analysis of discharge techniques for multiple battery systems. ISLPED 2003: 44-47 |

32 | EE | Daler N. Rakhmatov, Sarma B. K. Vrudhula: Energy management for battery-powered embedded systems. ACM Trans. Embedded Comput. Syst. 2(3): 277-324 (2003) |

31 | EE | Ravishankar Rao, Sarma B. K. Vrudhula, Daler N. Rakhmatov: Battery Modeling for Energy-Aware System Design. IEEE Computer 36(12): 77-87 (2003) |

30 | EE | Daler N. Rakhmatov, Sarma B. K. Vrudhula, Deborah A. Wallach: A model for battery lifetime analysis for organizing applications on a pocket computer. IEEE Trans. VLSI Syst. 11(6): 1019-1030 (2003) |

29 | EE | Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul: Probabilistic analysis of interconnect coupling noise. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1188-1203 (2003) |

2002 | ||

28 | EE | Daler N. Rakhmatov, Sarma B. K. Vrudhula: Hardware-software bipartitioning for dynamically reconfigurable systems. CODES 2002: 145-150 |

27 | EE | Daler N. Rakhmatov, Sarma B. K. Vrudhula, Chaitali Chakrabarti: Battery-conscious task sequencing for portable devices including voltage/clock scaling. DAC 2002: 189-194 |

26 | EE | Sarma B. K. Vrudhula, David Blaauw, Supamas Sirichotiyakul: Estimation of the likelihood of capacitive coupling noise. DAC 2002: 653-658 |

25 | EE | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Estimation of signal arrival times in the presence of delay noise. ICCAD 2002: 418-422 |

24 | EE | Daler N. Rakhmatov, Sarma B. K. Vrudhula, Deborah A. Wallach: Battery lifetime prediction for energy-aware computing. ISLPED 2002: 154-159 |

23 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 16-21 |

22 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 29-36 |

21 | EE | Haibo Wang, Sarma B. K. Vrudhula: Behavioral synthesis of field programmable analog array circuits. ACM Trans. Design Autom. Electr. Syst. 7(4): 563-604 (2002) |

20 | EE | Qi Wang,
Sarma B. K. Vrudhula:
Algorithms for minimizing standby power in deep submicrometer, dual-V_{t} CMOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 306-318 (2002) |

2001 | ||

19 | EE | Daler N. Rakhmatov, Sarma B. K. Vrudhula: An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems. ICCAD 2001: 488-493 |

18 | Daler N. Rakhmatov, Sarma B. K. Vrudhula: Minimizing routing configuration cost in dynamically reconfigurable FPGAs. IPDPS 2001: 145 | |

17 | EE | Daler N. Rakhmatov, Sarma B. K. Vrudhula: Time-to-failure estimation for batteries in portable electronic systems. ISLPED 2001: 88-91 |

2000 | ||

16 | EE | Daler N. Rakhmatov, Sarma B. K. Vrudhula, Thomas J. Brown, Ajay Nagarandal: Adaptive Multiuser Online Reconfigurable Engine. IEEE Design & Test of Computers 17(1): 53-67 (2000) |

1999 | ||

15 | EE | Qi Wang, Sarma B. K. Vrudhula: An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits. ICCD 1999: 556-562 |

14 | EE | Qi Wang, Sarma B. K. Vrudhula, Gary K. H. Yeap, Shantanu Ganguly: Power reduction and power-delay trade-offs using logic transformations. ACM Trans. Design Autom. Electr. Syst. 4(1): 97-121 (1999) |

1998 | ||

13 | EE | Qi Wang, Sarma B. K. Vrudhula: Data Driven Power Optimization of Sequential Circuits. DATE 1998: 686-691 |

12 | EE | Qi Wang, Sarma B. K. Vrudhula: Static power optimization of deep submicron CMOS circuits for dual VT technology. ICCAD 1998: 490-496 |

1997 | ||

11 | EE | Qi Wang, Sarma B. K. Vrudhula, Shantanu Ganguly: An Investigation of Power Delay Trade-Offs on PowerPC Circuits. DAC 1997: 425-428 |

1996 | ||

10 | EE | Qi Wang, Sarma B. K. Vrudhula: Multi-level logic optimization for low power using local logic transformations. ICCAD 1996: 270-277 |

9 | Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula: Formal Verification Using Edge-Valued Binary Decision Diagrams. IEEE Trans. Computers 45(2): 247-255 (1996) | |

1995 | ||

8 | Amitava Majumdar, Sarma B. K. Vrudhula: Fault Coverage and Test Length Estimation for Random Pattern Testing. IEEE Trans. Computers 44(2): 234-247 (1995) | |

1994 | ||

7 | EE | King C. Ho, Sarma B. K. Vrudhula: Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts. IEEE Trans. on CAD of Integrated Circuits and Systems 13(10): 1201-1222 (1994) |

6 | EE | Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula: EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition. IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 959-975 (1994) |

5 | EE | Amitava Majumdar, Sarma B. K. Vrudhula: Techniques for estimating test length under random test. J. Electronic Testing 5(2-3): 285-297 (1994) |

1993 | ||

4 | EE | Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula: BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis. DAC 1993: 642-647 |

3 | EE | Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula: FGILP: an integer linear program solver based on function graphs. ICCAD 1993: 685-689 |

2 | EE | T.-Y. Wuu, Sarma B. K. Vrudhula: A design of a fast and area efficient multi-input Muller C-element. IEEE Trans. VLSI Syst. 1(2): 215-219 (1993) |

1 | EE | Amitava Majumdar, Sarma B. K. Vrudhula: Analysis of signal probability in logic circuits using stochastic models. IEEE Trans. VLSI Syst. 1(3): 365-379 (1993) |