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Zvonko G. Vranesic Vis

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*2008
61EEFranjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown: Towards Compilation of Streaming Programs into FPGA Hardware. FDL 2008: 67-72
2007
60 Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown: On Digital Search Trees - A Simple Method for Constructing Balanced Binary Trees. ICSOFT (PL/DPS/KE/MUSE) 2007: 61-68
2006
59EEBlair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown: A Multithreaded Soft Processor for SoPC Area Reduction. FCCM 2006: 131-142
58EEValavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic: Adaptive FPGAs: High-Level Architecture and a Synthesis Method. FPL 2006: 1-8
57EEValavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic: Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2331-2340 (2006)
2005
56EEFranjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown: Experiences with Soft-Core Processor Design. IPDPS 2005
2003
55EEDebatosh Debnath, Zvonko G. Vranesic: A fast algorithm for OR-AND-OR synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1166-1176 (2003)
2002
54EEValavan Manohararajah, Terry Borer, Stephen Dean Brown, Zvonko G. Vranesic: Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. FPL 2002: 232-241
53EEZeljko Zilic, Zvonko G. Vranesic: A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields. IEEE Trans. Computers 51(9): 1100-1105 (2002)
2001
52EESteven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: Structural analysis and generation of synthetic digital circuits with memory. IEEE Trans. VLSI Syst. 9(1): 223-226 (2001)
2000
51EER. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: The NUMAchine Multiprocessor. ICPP 2000: 487-496
1999
50EESteven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: The memory/logic interface in FPGAs with large embedded memory arrays. IEEE Trans. VLSI Syst. 7(1): 80-91 (1999)
49 Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic: The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning. International Journal of Parallel Programming 27(5): 327-356 (1999)
1998
48EEA. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: Design and Implementation of the NUMAchine Multiprocessor. DAC 1998: 66-69
47EEZvonko G. Vranesic: The FPGA Challenge. ISMVL 1998: 121-
46 Zeljko Zilic, Zvonko G. Vranesic: Using Decision Diagrams to Design ULMs for FPGAs. IEEE Trans. Computers 47(9): 970-982 (1998)
1997
45EESteven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. FPGA 1997: 10-16
44EEKeith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic: Memory-System Design Considerations for Dynamically-Scheduled Processors. ISCA 1997: 133-143
43EEKeith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic: The Multicluster Architecture: Reducing Cycle Time Through Partitioning. MICRO 1997: 149-159
42 Sinisa Srbljic, Zvonko G. Vranesic, Michael Stumm, Leo Budin: Analytical Prediction of Performance for Cache Coherence Protocols. IEEE Trans. Computers 46(11): 1155-1173 (1997)
1996
41EEStephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic: Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. DAC 1996: 427-432
40EEZeljko Zilic, Zvonko G. Vranesic: Using BDDs to Design ULMs for FPGAs. FPGA 1996: 24-30
39EEZeljko Zilic, Zvonko G. Vranesic: New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. ISMVL 1996: 16-23
38EEStephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic: Minimizing FPGA Interconnect Delays. IEEE Design & Test of Computers 13(4): 16-23 (1996)
1995
37EEMuhammad Jaseemuddin, Zvonko G. Vranesic: Bidirectional Ring: An Alternative to the Hierarchy of Unidirectional Rings. Euro-Par 1995: 567-578
36EESteven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: Architecture of Centralized Field-Configurable Memory. FPGA 1995: 97-103
35EEZeljko Zilic, Zvonko G. Vranesic: Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. ISMVL 1995: 36-43
34 Zeljko Zilic, Zvonko G. Vranesic: A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions. IEEE Trans. Computers 44(8): 1012-1020 (1995)
1994
33 Sinisa Srbljic, Zvonko G. Vranesic, Leo Budin: Performance Prediction for Different Consistency Schemes in Distributed Shared Memory Systems. HPDC 1994: 295-302
32 Alireza Kaviani, Zvonko G. Vranesic: On Scheduling in Multiprocessor Systems Using Fuzzy Logic. ISMVL 1994: 141-147
1993
31 Zeljko Zilic, Zvonko G. Vranesic: Current-Mode CMOS Galois Field Circuits. ISMVL 1993: 245-250
30 Steven J. E. Wilton, Zvonko G. Vranesic: Architectural Support for Block Transfers in a Shared-Memory Multiprocessor. SPDP 1993: 51-55
29 Michiel van de Panne, Eugene Fiume, Zvonko G. Vranesic: Physically Based Modeling and Control of Turning. CVGIP: Graphical Model and Image Processing 55(6): 507-521 (1993)
28EEStephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic: A stochastic model to predict the routability of field-programmable gate arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1827-1838 (1993)
1992
27 Konrad Lei, Zvonko G. Vranesic: Towards the Realization of 4-Valued CMOS Circuits. ISMVL 1992: 104-110
26 Keith I. Farkas, Zvonko G. Vranesic, Michael Stumm: Cache Consistency in Hierarchical-Ring-Based Multiprocessors. SC 1992: 348-357
25EEStephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic: A detailed router for field-programmable gate arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 620-628 (1992)
1991
24EERobert J. Francis, Jonathan Rose, Zvonko G. Vranesic: Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs. DAC 1991: 227-233
23 Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic: Technology Mapping on Lookup Table-Based FPGAs for Performance. ICCAD 1991: 568-571
22 Zvonko G. Vranesic, V. Carl Hamacher, A. K. Sanwalka, Safwat G. Zaky: A Hybrid Token/Insertion Ring LAN. INFOCOM 1991: 211-220
21 Konrad Lei, Zvonko G. Vranesic: On the Synthesis of 4-Valued Current Mode CMOS Circuits. ISMVL 1991: 147-155
20 Zvonko G. Vranesic, Michael Stumm, David M. Lewis, Ron White: Hector: A Hierarchically Structured Shared-memory Multiprocessor. IEEE Computer 24(1): 72-79 (1991)
19 Mostafa H. Abd-El-Barr, Zvonko G. Vranesic, Safwat G. Zaky: Algorithmic Synthesis of MVL Functions for CCD Implementation. IEEE Trans. Computers 40(8): 977-986 (1991)
1990
18 Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic: A Detailed Router for Field-Programmable Gate Arrays. ICCAD 1990: 382-385
17 Lap-kong Chan, Zvonko G. Vranesic: TORMLAN - A Multichannel Local Area Network Protocol. INFOCOM 1990: 756-765
16 Safwat G. Zaky, Zvonko G. Vranesic, Mostafa H. Abd-El-Barr: Step-Wise Synthesis of CCD MVL Functions. ISMVL 1990: 300-307
15EEMichiel van de Panne, Eugene Fiume, Zvonko G. Vranesic: Reusable motion synthesis using state-space controllers. SIGGRAPH 1990: 225-234
14 Mostafa H. Abd-El-Barr, Zvonko G. Vranesic: Cost Reduction in the CCD Realization of MVMT Function. IEEE Trans. Computers 39(5): 702-706 (1990)
1988
13EEJonathan Rose, W. Martin Snelgrove, Zvonko G. Vranesic: Parallel standard cell placement algorithms with quality equivalent to simulated annealing. IEEE Trans. on CAD of Integrated Circuits and Systems 7(3): 387-396 (1988)
1986
12 Wayne M. Loucks, William I. Kwak, Zvonko G. Vranesic: Implementation of a Dynamic Address Assignment Protocol in a Local Area Network. Computer Networks 11: 133-146 (1986)
11 Mostafa H. Abd-El-Barr, Safwat G. Zaky, Zvonko G. Vranesic: Synthesis of Multivalued Multithreshold Functions for CCD Implementation. IEEE Trans. Computers 35(2): 124-133 (1986)
1984
10 Kuang-Wei Chiang, Zvonko G. Vranesic: Comments on ``Fault Diagnosis of MOS Combinational Networks''. IEEE Trans. Computers 33(10): 947 (1984)
1983
9 Paul Chow, Zvonko G. Vranesic, Jui Lin Yen: A Pipelined Distributed Arithmetic PFFT Processor. IEEE Trans. Computers 32(12): 1128-1136 (1983)
8 Kuang-Wei Chiang, Zvonko G. Vranesic: A Tree Representation of Combinational Networks. IEEE Trans. Computers 32(3): 315-319 (1983)
1981
7 C. L. Lam, Zvonko G. Vranesic: Key compression using segment strings. Inf. Syst. 6(2): 139-146 (1981)
1980
6 H. T. Mouftah, K. C. Smith, Zvonko G. Vranesic: Ternary Rate-Multipliers. IEEE Trans. Computers 29(10): 929-931 (1980)
1978
5 A. Druzeta, Zvonko G. Vranesic: A. Higher Radix Technique for Fault Detection in Many-Valued Multithreshold Networks. IEEE Trans. Computers 27(11): 1070-1073 (1978)
1977
4 Zvonko G. Vranesic: Multiple-Valued Logic: An Introduction and Overview. IEEE Trans. Computers 26(12): 1181-1182 (1977)
1973
3 Zvonko G. Vranesic, V. Carl Hamacher, Y. Y. Leung: Design of a Fully Variable - Length Structured Minicomputer. ISCA 1973: 251-255
1972
2EEZvonko G. Vranesic, V. Carl Hamacher: Ternary logic in parallel multipliers. Comput. J. 15(3): 254-258 (1972)
1970
1 K. M. Waliuzzaman, Zvonko G. Vranesic: On Decomposition of Multi-Valued Switching Functions. Comput. J. 13(4): 359-362 (1970)

Coauthor Index

1Mostafa H. Abd-El-Barr [11] [14] [16] [19]
2Tarek S. Abdelrahman [51]
3Terry Borer [54]
4Stephen Dean Brown [18] [25] [28] [38] [41] [48] [51] [54] [56] [57] [58] [59] [60] [61]
5Leo Budin [33] [42]
6Davor Capalija [59]
7S. Caranci [41] [48] [51]
8Lap-kong Chan [17]
9Kuang-Wei Chiang [8] [10]
10Paul Chow [9] [43] [44] [49]
11D. DeVries [51]
12Debatosh Debnath [55]
13A. Druzeta [5]
14Keith I. Farkas [26] [43] [44] [49]
15Eugene Fiume [15] [29]
16Blair Fort [56] [59]
17Robert J. Francis [23] [24]
18Benjamin Gamsa [51]
19A. Grbic [41] [48] [51]
20R. Grindley [41] [48] [51]
21M. Gusat [41] [48] [51]
22V. Carl Hamacher [2] [3] [22]
23R. Ho [51]
24Muhammad Jaseemuddin [37]
25Norman P. Jouppi [43] [44] [49]
26Alireza Kaviani [32]
27Muhammad M. Khellah [38]
28Orran Krieger [51]
29William I. Kwak [12]
30C. L. Lam [7]
31Konrad Lei [21] [27]
32Guy G. Lemieux [48] [51]
33Y. Y. Leung [3]
34David M. Lewis [20]
35Wayne M. Loucks [12]
36K. Loveless [41] [48] [51]
37Naraig Manjikian [41] [48] [51]
38Valavan Manohararajah [54] [57] [58]
39P. McHardy [51]
40H. T. Mouftah (Hussein T. Mouftah) [6]
41Michiel van de Panne [15] [29]
42Franjo Plavec [56] [60] [61]
43Jonathan Rose [13] [18] [23] [24] [25] [28] [36] [45] [50] [52]
44A. K. Sanwalka [22]
45K. C. Smith [6]
46W. Martin Snelgrove [13]
47Sinisa Srbljic [33] [41] [42] [48] [51]
48Michael Stumm [20] [26] [42] [48] [51]
49K. M. Waliuzzaman [1]
50Ron White [20]
51Steven J. E. Wilton [30] [36] [45] [50] [52]
52Jui Lin Yen [9]
53Safwat G. Zaky [11] [16] [19] [22]
54Zeljko Zilic [31] [34] [35] [39] [40] [41] [46] [48] [51] [53]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)