| 1996 |
|---|
| 5 | EE | Mohan Vishwanath,
Robert Michael Owens:
A Common Architecture For The DWT and IDWT.
ASAP 1996: 193-198 |
| 4 | EE | Navin Chaddha,
Mohan Vishwanath:
A low power video encoder with power, memory and bandwidth scalability.
VLSI Design 1996: 358-363 |
| 1995 |
|---|
| 3 | | Navin Chaddha,
Mohan Vishwanath,
Philip A. Chou:
Hierarchical Vector Quantization of Perceptually Weighted Block Transforms.
Data Compression Conference 1995: 3-12 |
| 1994 |
|---|
| 2 | | Mohan Vishwanath,
Philip A. Chou:
An Efficient Algorithm for Hierarchical Compression of Video.
ICIP (3) 1994: 275-279 |
| 1993 |
|---|
| 1 | EE | Robert Michael Owens,
Thomas P. Kelliher,
Mary Jane Irwin,
Mohan Vishwanath,
Raminder Singh Bajwa,
W.-L. Yang:
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system.
IEEE Trans. VLSI Syst. 1(4): 491-502 (1993) |
