Massimo Violante

2007
72	EE	Luca Sterpone, Massimo Violante: A new decompression system for the configuration process of SRAM-based FPGAS. ACM Great Lakes Symposium on VLSI 2007: 241-246
71	EE	Luca Sterpone, Massimo Violante: A new hardware architecture for performing the gridding of DNA microarray images. ACM Great Lakes Symposium on VLSI 2007: 341-346
70	EE	Luca Sterpone, Massimo Violante: Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs. European Test Symposium 2007: 159-164
69	EE	Salvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante: Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. IOLTS 2007: 194-196
68	EE	Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro: Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. J. Electronic Testing 23(1): 47-54 (2007)
2006
67	EE	Maurizio Martina, Guido Masera, Andrea Molino, Fabrizio Vacca, Luca Sterpone, Massimo Violante: A new approach to compress the configuration information of programmable devices. DATE Designers' Forum 2006: 48-51
66		Luca Sterpone, Massimo Violante: ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications. DDECS 2006: 54-58
65	EE	Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto: Combined software and hardware techniques for the design of reliable IP processors. DFT 2006: 265-273
64	EE	Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante: Online hardening of programs against SEUs and SETs. DFT 2006: 280-290
63	EE	Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena: Fault Injection-based Reliability Evaluation of SoPCs. European Test Symposium 2006: 75-82
62	EE	Luca Sterpone, Massimo Violante: Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices. IOLTS 2006: 189-190
61	EE	Matteo Sonza Reorda, Massimo Violante: Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems. IOLTS 2006: 229-234
60	EE	Paolo Bernardi, Leticia Maria Veiras Bolzani, Alberto Manzone, Marcella Guagliumi Massimo Osella, Massimo Violante, Matteo Sonza Reorda: Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. MTV 2006: 3-8
59	EE	Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante: Early, Accurate Dependability Analysis of CAN-Based Networked Systems. IEEE Design & Test of Computers 23(1): 38-45 (2006)
58	EE	Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante: A New Hybrid Fault Detection Technique for Systems-on-a-Chip. IEEE Trans. Computers 55(2): 185-198 (2006)
57	EE	Luca Sterpone, Massimo Violante: A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs. IEEE Trans. Computers 55(6): 732-744 (2006)
2005
56	EE	Luca Sterpone, Massimo Violante: A design flow for protecting FPGA-based systems against single event upsets. DFT 2005: 436-444
55	EE	Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. DFT 2005: 445-453
54	EE	Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante: On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. DSN 2005: 50-58
53	EE	Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero, Luca Sterpone, Massimo Violante: New evolutionary techniques for test-program generation for complex microprocessor cores. GECCO 2005: 2193-2194
52	EE	Matteo Sonza Reorda, Luca Sterpone, Massimo Violante: Efficient Estimation of SEU Effects in SRAM-Based FPGAs. IOLTS 2005: 54-59
51	EE	Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante: Automatic generation of test sets for SBST of microprocessor IP cores. SBCCI 2005: 74-79
2004
50	EE	O. Goloubeva, Matteo Sonza Reorda, Massimo Violante: Automatic Generation of Validation Stimuli for Application-Specific Processors. DATE 2004: 188-193
49	EE	M. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin: Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA. DATE 2004: 584-589
48	EE	Matteo Sonza Reorda, Massimo Violante: On-Line Analysis and Perturbation of CAN Networks. DFT 2004: 424-432
47	EE	Ernesto Sánchez, Giovanni Squillero, Massimo Violante: Exploiting HW Acceleration for Classifying Complex Test Program Generation Problems. EvoWorkshops 2004: 230-239
46	EE	Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante: On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. IOLTS 2004: 115-120
45	EE	Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante: Hybrid Soft Error Detection by Means of Infrastructure IP Cores. IOLTS 2004: 79-88
44	EE	Fulvio Corno, Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante: A multi-level approach to the dependability analysis of networked systems based on the CAN protocol. SBCCI 2004: 71-75
43	EE	Matteo Sonza Reorda, Massimo Violante: Efficient analysis of single event transients. Journal of Systems Architecture 50(5): 239-246 (2004)
2003
42	EE	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor. DATE 2003: 10602-10607
41	EE	Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories. DATE 2003: 10720-10725
40	EE	Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante: Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. DFT 2003: 336-343
39	EE	J. Pérez, Matteo Sonza Reorda, Massimo Violante: Dependability Analysis of CAN Networks: An Emulation-Based Approach. DFT 2003: 537-
38	EE	O. Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Soft-Error Detection Using Control Flow Assertions. DFT 2003: 581-588
37	EE	Matteo Sonza Reorda, Massimo Violante: Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits. FPL 2003: 616-626
36	EE	Matteo Sonza Reorda, Massimo Violante: Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits. IOLTS 2003: 101-105
35	EE	Massimo Violante, M. Ceschia, Matteo Sonza Reorda, A. Paccagnella, Paolo Bernardi, Maurizio Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori: Analyzing SEU Effects in SRAM-based FPGAs. IOLTS 2003: 119-123
34	EE	O. Goloubeva, Matteo Sonza Reorda, Massimo Violante: An RT-level Concurrent Error Detection Technique for Data Dominated Systems. IOLTS 2003: 159
33	EE	Davide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante: Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. ITC 2003: 379-385
32	EE	J. Pérez, Matteo Sonza Reorda, Massimo Violante: Accurate Dependability Analysis of CAN-Based Networked Systems. SBCCI 2003: 337-342
31	EE	Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: New techniques for efficiently assessing reliability of SOCs. Microelectronics Journal 34(1): 53-61 (2003)
2002
30	EE	Matteo Sonza Reorda, Massimo Violante: Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments. DFT 2002: 263-274
29	EE	Pierluigi Civera, Luca Macchiarulo, Massimo Violante: A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis. DFT 2002: 31-39
28	EE	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: A New Functional Fault Model for FPGA Application-Oriented Testing. DFT 2002: 372-380
27	EE	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs. FPL 2002: 607-615
26	EE	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Analysis of SEU Effects in a Pipelined Processor. IOLTW 2002: 112-116
2001
25	EE	Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: FPGA-Based Fault Injection for Microprocessor Systems. Asian Test Symposium 2001: 304-
24	EE	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante: On the test of microprocessor IP cores. DATE 2001: 209-213
23	EE	Ph. Cheynet, B. Nicolescu, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: System safety through automatic high-level code transformations: an experimental evaluation. DATE 2001: 297-301
22	EE	Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . DFT 2001: 250-258
21	EE	Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. FPL 2001: 493-502
20	EE	Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting FPGA for Accelerating Fault Injection Experiments. IOLTW 2001: 9-13
19	EE	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Marco Torchiano: A Source-to-Source Compiler for Generating Dependable Software. SCAM 2001: 35-44
18	EE	Marcello Lajolo, Matteo Sonza Reorda, Massimo Violante: Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. VLSI Design 2001: 371-
2000
17	EE	Marcello Lajolo, Luciano Lavagno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Automatic test bench generation for simulation-based validation. CODES 2000: 136-140
16	EE	Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno: Evaluating System Dependability in a Co-Design Framework. DATE 2000: 586-590
15	EE	Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante: An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications. DFT 2000: 257-265
14		Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Prediction of Power Requirements for High-Speed Circuits. EvoWorkshops 2000: 247-254
13	EE	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante: A genetic algorithm-based system for generating test programs for microprocessor IP cores. ICTAI 2000: 195-198
12	EE	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Ph. Cheynet, B. Nicolescu, Raoul Velazco: Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. IOLTW 2000: 17-
11	EE	B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: New Techniques for Accelerating Fault Injection in VHDL Descriptions. IOLTW 2000: 61-66
10	EE	Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda, Massimo Violante: Early Power Estimation for System-on-Chip Designs. PATMOS 2000: 108-117
9	EE	B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Speeding-Up Fault Injection Campaigns in VHDL Models. SAFECOMP 2000: 27-36
8	EE	Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante: Low Power BIST via Non-Linear Hybrid Cellular Automata. VTS 2000: 29-34
1999
7	EE	Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante: Soft-Error Detection through Software Fault-Tolerance Techniques. DFT 1999: 210-218
6	EE	Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante: Optimal Vector Selection for Low Power BIST. DFT 1999: 219-226
5		Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Test Pattern Generation Under Low Power Constraints. EvoWorkshops 1999: 162-170
4	EE	Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: ALPS: A Peak Power Estimation Tool for Sequential Circuits. Great Lakes Symposium on VLSI 1999: 350-353
3	EE	Fulvio Corno, Uwe Gläser, Paolo Prinetto, Matteo Sonza Reorda, Heinrich Theodor Vierhaus, Massimo Violante: SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 191-202 (1999)
1998
2	EE	Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante: Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection. DATE 1998: 670-
1997
1	EE	Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG. Asian Test Symposium 1997: 68-73

Coauthor Index

1	Julio Pérez Acle	[44] [59]
2	Abdelaziz Ammari	[40]
3	Davide Appello	[33]
4	M. Bellato	[35] [49]
5	Paolo Bernardi	[33] [35] [41] [46] [49] [54] [55] [58] [60]
6	Cristiana Bolchini	[65]
7	Leticia Maria Veiras Bolzani	[45] [54] [55] [58] [60]
8	D. Bortolato	[35] [49]
9	A. Candelori	[35] [49]
10	Gian-Carlo Cardarilli	[69]
11	Luigi Carro	[64] [68]
12	M. Ceschia	[35] [49]
13	Ph. Cheynet	[12] [23]
14	Pierluigi Civera	[20] [21] [22] [25] [29] [31]
15	Fulvio Corno	[1] [2] [3] [4] [5] [6] [8] [13] [14] [24] [44]
16	Luis Entrena (Luis Entrena-Arrontes)	[63]
17	Alessandra Fudoli	[33]
18	Uwe Gläser	[3]
19	O. Goloubeva	[34] [38] [50]
20	Fernanda Gusmão de Lima Kastensmidt (Fernanda Gusmão de Lima, Fernanda Lima Kastensmidt)	[68]
21	Marcello Lajolo	[10] [16] [17] [18]
22	Luciano Lavagno	[10] [16] [17]
23	Régis Leveugle	[40]
24	Carlos Arthur Lang Lisbôa	[64]
25	Celia López-Ongil	[63]
26	Luca Macchiarulo	[20] [21] [22] [25] [29] [31]
27	Alberto Manzone	[60]
28	Maurizio Martina	[67]
29	Guido Masera	[67]
30	Antonio Miele	[65]
31	Andrea Molino	[67]
32	B. Nicolescu	[12] [23]
33	Marcella Guagliumi Massimo Osella	[60]
34	A. Paccagnella	[35] [49]
35	B. Parrotta	[9] [11]
36	J. Pérez	[32] [39]
37	Salvatore Pontarelli	[69]
38	Marta Portela-García	[63]
39	Paolo Prinetto	[1] [2] [3]
40	Marco Re	[69]
41	Maurizio Rebaudengo	[1] [4] [5] [6] [7] [8] [9] [11] [12] [14] [15] [16] [17] [19] [20] [21] [22] [23] [25] [26] [27] [28] [31] [33] [35] [38] [41] [42] [45] [49] [54] [55] [58] [65]
42	Matteo Sonza Reorda	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [48] [49] [50] [51] [52] [53] [54] [55] [58] [59] [60] [61] [63] [64] [68] [69]
43	Adelio Salsano	[69]
44	Ernesto Sánchez (Edgar Ernesto Sánchez Sánchez)	[47] [51] [53]
45	Massimiliano Schillaci	[53]
46	Donatella Sciuto	[65]
47	Giovanni Squillero	[8] [13] [24] [47] [51] [53]
48	Luca Sterpone	[46] [52] [53] [56] [57] [62] [63] [65] [66] [67] [68] [69] [70] [71] [72]
49	Vincenzo Tancorre	[33]
50	Marco Torchiano	[7] [15] [19]
51	Fabrizio Vacca	[67]
52	Fabian Vargas	[45] [54] [58]
53	Raoul Velazco	[12] [23]
54	Heinrich Theodor Vierhaus	[3]
55	P. Zambolin	[35] [49]