| 2004 |
|---|
| 44 | EE | Xiaoyun Sun,
Larry L. Kinney,
Bapiraju Vinnakota:
Combining dictionary coding and LFSR reseeding for test data compression.
DAC 2004: 944-947 |
| 2003 |
|---|
| 43 | EE | Xiaoyun Sun,
Larry L. Kinney,
Bapiraju Vinnakota:
Test Vector Generation Based on Correlation Model for Ratio-Iddq.
ITC 2003: 545-554 |
| 42 | EE | Xiaoyun Sun,
Larry L. Kinney,
Bapiraju Vinnakota:
Development of Energy Consumption Ratio Test.
VTS 2003: 279-286 |
| 2002 |
|---|
| 41 | EE | Wanli Jiang,
Bapiraju Vinnakota:
Statistical threshold formulation for dynamic Idd test.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(6): 694-705 (2002) |
| 2001 |
|---|
| 40 | EE | Xiaoyun Sun,
Seonki Kim,
Bapiraju Vinnakota:
Crosstalk Fault Detection by Dynamic Idd.
ICCAD 2001: 375- |
| 39 | | Amit K. Varshney,
Bapiraju Vinnakota,
Eric Skuldt,
Brion L. Keller:
High Performance Parallel Fault Simulation.
ICCD 2001: 308-313 |
| 38 | EE | Wooyoung Choi,
Ramesh Harjani,
Bapiraju Vinnakota:
Non-ideal amplifier effects on the accuracy of analog-to-digital capacitor ratio converter.
ISCAS (1) 2001: 552-555 |
| 37 | EE | Xiaoyun Sun,
Bapiraju Vinnakota:
Current Measurement for Dynamic Idd Test.
VTS 2001: 117-123 |
| 36 | EE | Wanli Jiang,
Bapiraju Vinnakota:
Defect-oriented test scheduling.
IEEE Trans. VLSI Syst. 9(3): 427-438 (2001) |
| 2000 |
|---|
| 35 | EE | Wooyoung Choi,
Ramesh Harjani,
Bapiraju Vinnakota:
Optimal test-set generation for parametric fault detection in switched capacitor filters.
Asian Test Symposium 2000: 72-77 |
| 34 | | Seonki Kim,
Bapiraju Vinnakota:
Fast Test Application Technique Without Fast Scan Clocks.
ICCAD 2000: 464-467 |
| 33 | | Seonki Kim,
Sreejit Chakravarty,
Bapiraju Vinnakota:
An analysis of the delay defect detection capability of the ECR test method.
ITC 2000: 1060-1069 |
| 32 | EE | Bapiraju Vinnakota,
André Ivanov:
Biomedical ICs: What is Different about Testing those ICs?
VTS 2000: 329-332 |
| 31 | EE | Wanli Jiang,
Bapiraju Vinnakota:
IC test using the energy consumption ratio.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 129-141 (2000) |
| 30 | EE | Bapiraju Vinnakota,
Ramesh Harjani:
DFT for digital detection of analog parametric faults in SC filters.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 789-798 (2000) |
| 1999 |
|---|
| 29 | EE | Ramesh Harjani,
Bapiraju Vinnakota:
Digital Aetection of Analog Parametric Faults in SC Filters.
DAC 1999: 772-777 |
| 28 | EE | Wanli Jiang,
Bapiraju Vinnakota:
IC Test Using the Energy Consumption Ratio.
DAC 1999: 976-981 |
| 27 | EE | Bapiraju Vinnakota:
Deep submicron defect detection with the energy consumption ratio.
ICCAD 1999: 467-470 |
| 26 | | Wanli Jiang,
Bapiraju Vinnakota:
Statistical threshold formulation for dynamic I_dd test.
ITC 1999: 57-66 |
| 25 | EE | Wanli Jiang,
Bapiraju Vinnakota:
Defect-Oriented Test Scheduling.
VTS 1999: 433-439 |
| 24 | EE | Minesh B. Amin,
Bapiraju Vinnakota:
Data parallel fault simulation.
IEEE Trans. VLSI Syst. 7(2): 183-190 (1999) |
| 1998 |
|---|
| 23 | EE | Dechang Sun,
Bapiraju Vinnakota,
Wanli Jiang:
Fast State Verification.
DAC 1998: 619-624 |
| 22 | EE | Bapiraju Vinnakota,
Wanli Jiang,
Dechang Sun:
Process-tolerant test with energy consumption ratio.
ITC 1998: 1027-1036 |
| 21 | EE | Bapiraju Vinnakota,
Jason Andrews:
Fast fault translation.
IEEE Trans. VLSI Syst. 6(1): 122-133 (1998) |
| 1997 |
|---|
| 20 | EE | Bapiraju Vinnakota,
Ramesh Harjani,
Wooyoung Choi:
Pseudoduplication - An ACOB Technique for Single-Ended Circuits.
VLSI Design 1997: 398-402 |
| 1996 |
|---|
| 19 | EE | Minesh B. Amin,
Bapiraju Vinnakota:
Zamlog: a parallel algorithm for fault simulation based on Zambezi.
ICCAD 1996: 509-512 |
| 18 | EE | Bapiraju Vinnakota,
Ramesh Harjani:
Mixed-Signal Design for Test.
VLSI Design 1996: 2 |
| 17 | EE | Minesh B. Amin,
Bapiraju Vinnakota:
ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator.
VTS 1996: 438-443 |
| 16 | EE | Bapiraju Vinnakota:
Monitoring power dissipation for fault detection.
VTS 1996: 483-488 |
| 1995 |
|---|
| 15 | EE | Bapiraju Vinnakota,
Ramesh Harjani,
Nicholas J. Stessman:
System-Level Design for Test of Fully Differential Analog Circuits.
DAC 1995: 450-454 |
| 14 | EE | Minesh B. Amin,
Bapiraju Vinnakota:
Data parallel fault simulation.
ICCD 1995: 610-615 |
| 13 | EE | Bapiraju Vinnakota,
Nicholas J. Stessman:
Reducing test application time in scan design schemes.
VTS 1995: 367-373 |
| 12 | | Bapiraju Vinnakota:
Implementing Multiplication with Split Read-Only Memory.
IEEE Trans. Computers 44(11): 1352-1356 (1995) |
| 1994 |
|---|
| 11 | EE | Bapiraju Vinnakota,
Jason Andrews:
Functional Test Generation for FSMs by Fault Extraction.
DAC 1994: 712-715 |
| 10 | | Bapiraju Vinnakota,
Ramesh Harjani:
The Design of Analog Self-Checking Circuits.
VLSI Design 1994: 67-70 |
| 9 | | Bapiraju Vinnakota,
V. V. Bapeswara Rao:
Generation of All Reed-Muller Expansions of a Switching Function.
IEEE Trans. Computers 43(1): 122-124 (1994) |
| 8 | EE | Bapiraju Vinnakota,
Niraj K. Jha:
Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis.
IEEE Trans. Parallel Distrib. Syst. 5(10): 1099-1106 (1994) |
| 7 | EE | Hosahalli R. Srinivas,
Bapiraju Vinnakota,
Keshab K. Parhi:
A C-testable carry-free divider.
IEEE Trans. VLSI Syst. 2(4): 472-488 (1994) |
| 6 | | Bapiraju Vinnakota,
V. V. Bapeswara Rao:
Enumeration of Binary Trees.
Inf. Process. Lett. 51(3): 125-127 (1994) |
| 1993 |
|---|
| 5 | | Hosahalli R. Srinivas,
Bapiraju Vinnakota,
Keshab K. Parhi:
A C-Testable Carry-Free Divider.
ICCD 1993: 206-213 |
| 4 | | Bapiraju Vinnakota,
Niraj K. Jha:
Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems.
IEEE Trans. Computers 42(8): 924-937 (1993) |
| 3 | EE | Bapiraju Vinnakota,
Niraj K. Jha:
Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs.
IEEE Trans. Parallel Distrib. Syst. 4(8): 864-874 (1993) |
| 1992 |
|---|
| 2 | | Bapiraju Vinnakota,
Jason Andrews:
Repair of RAMs With Clustered Faults.
ICCD 1992: 582-585 |
| 1991 |
|---|
| 1 | | Bapiraju Vinnakota,
Niraj K. Jha:
Design of Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis.
FTCS 1991: 504-511 |
