Kimiyoshi Usami

2007
13	EE	Kimiyoshi Usami: Overview on Low Power SoC Design Technology. ASP-DAC 2007: 634-636
2006
12	EE	Naoaki Ohkubo, Kimiyoshi Usami: Delay modeling and static timing analysis for MTCMOS circuits. ASP-DAC 2006: 570-575
11	EE	Kimiyoshi Usami, Naoaki Ohkubo: A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals. ICCD 2006
10	EE	Naoaki Ohkubo, Kimiyoshi Usami: Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits. IEICE Transactions 89-A(12): 3482-3490 (2006)
2002
9	EE	Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa: Automated selective multi-threshold design for ultra-low standby applications. ISLPED 2002: 202-206
8	EE	Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak: Code Coverage-Based Power Estimation Techniques for Microprocessors. Journal of Circuits, Systems, and Computers 11(5): 557- (2002)
2000
7	EE	Kimiyoshi Usami, Mutsunori Igarashi: Low-power design methodology and applications utilizing dual supply voltages. ASP-DAC 2000: 123-128
6	EE	Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak: Function-level power estimation methodology for microprocessors. DAC 2000: 810-813
1998
5		Takeshi Kitahara, Fumihiro Minami, Toshiaki Ueda, Kimiyoshi Usami, Seiichi Nishio, Masami Murakata, Takashi Mitsuhashi: A Clock-Gating Method for Low-Power LSI Design. ASP-DAC 1998: 307-312
4	EE	Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda: Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. DAC 1998: 483-488
1997
3	EE	Mutsunori Igarashi, Kimiyoshi Usami, Kazutaka Nogami, Fumihiro Minami, Yukio Kawasaki, Takahiro Aoki, Midori Takano, Chiharo Mizuno, Takashi Ishikawa, Masahiro Kanazawa, Shinji Sonoda, Makoto Ichida, Naoyuki Hatanaka: A low-power design method using multiple supply voltages. ISLPED 1997: 36-41
1995
2	EE	Kimiyoshi Usami, Mark Horowitz: Clustered voltage scaling technique for low-power design. ISLPD 1995: 3-8
1990
1	EE	Nobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori: Datapath Generator Based on Gate-Level Symbolic Layout. DAC 1990: 388-393

Coauthor Index

1	Takahiro Aoki	[3]
2	Hideho Arakida	[4]
3	Toshiyuki Furusawa	[9]
4	Mototsugu Hamada	[4]
5	Hiroshi Hatada	[1]
6	Naoyuki Hatanaka	[3]
7	Mark Horowitz	[2]
8	Makoto Ichida	[3]
9	Mutsunori Igarashi	[3] [4] [7]
10	Takashi Ishikawa	[3] [4]
11	Masahiro Kanazawa	[3] [4]
12	Naoyuki Kawabe	[6] [8] [9]
13	Yukio Kawasaki	[3]
14	Takeshi Kitahara	[5]
15	Masayuki Koizumi	[9]
16	Tadahiro Kuroda	[4]
17	Nobu Matsumoto	[1]
18	Fumihiro Minami	[3] [5]
19	Takashi Mitsuhashi	[5]
20	Chiharo Mizuno	[3]
21	Shojiro Mori	[1]
22	Masami Murakata	[5]
23	Seiichi Nishio	[5]
24	Kazutaka Nogami	[3]
25	Naoaki Ohkubo	[10] [11] [12]
26	Miodrag Potkonjak	[6] [8]
27	Gang Qu	[6] [8]
28	Katsuhiro Seta	[9]
29	Shinji Sonoda	[3]
30	Yukio Sugeno	[1]
31	Masafumi Takahashi	[4]
32	Midori Takano	[3]
33	Toshihiro Terazawa	[4]
34	Toshiaki Ueda	[5]
35	Yoko Watanabe	[1]

Colors in the list of coauthors