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Nur A. Touba Vis

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*2008
98EEJoon-Sung Yang, Nur A. Touba: Enhancing Silicon Debug via Periodic Monitoring. DFT 2008: 125-133
97EEJoon-Sung Yang, Nur A. Touba: Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture. VTS 2008: 345-351
96EERitesh Garg, Richard Putman, Nur A. Touba: Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation. VTS 2008: 35-42
95EEScott Davidson, Nur A. Touba: Guest Editors' Introduction: Progress in Test Compression. IEEE Design & Test of Computers 25(2): 112-113 (2008)
94EENur A. Touba: ITC 2008 Highlights. IEEE Design & Test of Computers 25(5): 398-399 (2008)
93EENur A. Touba, Adelio Salsano, Minsu Choi: Guest Editorial. J. Electronic Testing 24(1-3): 9-10 (2008)
2007
92 Cristiana Bolchini, Yong-Bin Kim, Adelio Salsano, Nur A. Touba: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy. IEEE Computer Society 2007
91EEAvijit Dutta, Nur A. Touba: Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code. DFT 2007: 3-11
90EERichard Putman, Nur A. Touba: Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression. VTS 2007: 211-218
89EEAvijit Dutta, Nur A. Touba: Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code. VTS 2007: 349-354
88EEKedarnath J. Balakrishnan, Nur A. Touba: Relationship Between Entropy and Test Data Compression. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 386-395 (2007)
87EEJinkyu Lee, Nur A. Touba: LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 396-401 (2007)
2006
86EEAvijit Dutta, Nur A. Touba: Synthesis of Efficient Linear Test Pattern Generators. DFT 2006: 206-214
85EEJinkyu Lee, Nur A. Touba: Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding. VTS 2006: 252-257
84EEAvijit Dutta, Nur A. Touba: Iterative OPDD Based Signal Probability Calculation. VTS 2006: 72-77
83EENur A. Touba: Survey of Test Vector Compression Techniques. IEEE Design & Test of Computers 23(4): 294-303 (2006)
82EEKedarnath J. Balakrishnan, Nur A. Touba: Improving Linear Test Data Compression. IEEE Trans. VLSI Syst. 14(11): 1227-1237 (2006)
81EEEric MacDonald, Nur A. Touba: Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits. IEEE Trans. VLSI Syst. 14(6): 587-595 (2006)
2005
80EEKedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil: Compressing Functional Tests for Microprocessors. Asian Test Symposium 2005: 428-433
79EEKedarnath J. Balakrishnan, Nur A. Touba: Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination. DATE 2005: 1130-1135
78EEJinkyu Lee, Nur A. Touba: Low Power BIST Based on Scan Partitioning. DFT 2005: 33-41
77EESamuel I. Ward, Chris Schattauer, Nur A. Touba: Using Statistical Transformations to Improve Compression for Linear Decompressors. DFT 2005: 42-50
76EEAvijit Dutta, Terence Rodrigues, Nur A. Touba: Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier. ISVLSI 2005: 200-205
75EEShalini Ghosh, Sugato Basu, Nur A. Touba: Synthesis of Low Power CED Circuits Based on Parity Codes. VTS 2005: 315-320
74EEShalini Ghosh, Sugato Basu, Nur A. Touba: Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits. J. Low Power Electronics 1(1): 63-72 (2005)
2004
73EEShalini Ghosh, Eric MacDonald, Sugato Basu, Nur A. Touba: Low-power weighted pseudo-random BIST using special scan cells. ACM Great Lakes Symposium on VLSI 2004: 86-91
72EEJinkyu Lee, Nur A. Touba: Low Power Test Data Compression Based on LFSR Reseeding. ICCD 2004: 180-185
71EEShalini Ghosh, Nur A. Touba, Sugato Basu: Reducing Power Consumption in Memory ECC Checkers. ITC 2004: 1322-1331
70EEKedarnath J. Balakrishnan, Nur A. Touba: Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion. ITC 2004: 936-944
69EEC. V. Krishna, Nur A. Touba: 3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme. VTS 2004: 79-86
68EEC. V. Krishna, Abhijit Jas, Nur A. Touba: Achieving high encoding efficiency with partial dynamic LFSR reseeding. ACM Trans. Design Autom. Electr. Syst. 9(4): 500-516 (2004)
67EEKartik Mohanram, Nur A. Touba: Lowering power consumption in concurrent checkers via input ordering. IEEE Trans. VLSI Syst. 12(11): 1234-1243 (2004)
66EEAbhijit Jas, C. V. Krishna, Nur A. Touba: Weighted pseudorandom hybrid BIST. IEEE Trans. VLSI Syst. 12(12): 1277-1283 (2004)
65EEAbhijit Jas, Bahram Pouya, Nur A. Touba: Test data compression technique for embedded cores using virtual scan chains. IEEE Trans. VLSI Syst. 12(7): 775-781 (2004)
64EEKedarnath J. Balakrishnan, Nur A. Touba: Matrix-based software test data decompression for systems-on-a-chip. Journal of Systems Architecture 50(5): 247-256 (2004)
2003
63EEKedarnath J. Balakrishnan, Nur A. Touba: Scan-Based BIST Diagnosis Using an Embedded Processor. DFT 2003: 209-216
62EEC. V. Krishna, Nur A. Touba: Hybrid BIST Using an Incrementally Guided LFSR. DFT 2003: 217-224
61EEKartik Mohanram, Nur A. Touba: Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits. DFT 2003: 433-
60EEC. V. Krishna, Nur A. Touba: Adjustable Width Linear Combinational Scan Vector Decompression. ICCAD 2003: 863-866
59EEKartik Mohanram, Egor S. Sogomonyan, Michael Gössel, Nur A. Touba: Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits. IOLTS 2003: 35-
58EEShalini Ghosh, Sugato Basu, Nur A. Touba: Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering. ISVLSI 2003: 246-249
57EEKartik Mohanram, Nur A. Touba: Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. ITC 2003: 893-901
56EEKartik Mohanram, Nur A. Touba: Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. VTS 2003: 121-127
55EEKedarnath J. Balakrishnan, Nur A. Touba: Deterministic Test Vector Decompression in Software Using Linear Operations. VTS 2003: 225-231
54EELei Li, Krishnendu Chakrabarty, Nur A. Touba: Test data compression using dictionaries with selective entries and fixed-length indices. ACM Trans. Design Autom. Electr. Syst. 8(4): 470-490 (2003)
53EEAbhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba: An efficient test vector compression scheme using selective Huffman coding. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 797-806 (2003)
2002
52EERanganathan Sankaralingam, Nur A. Touba: Reducing Test Power During Test Using Programmable Scan Chain Disable. DELTA 2002: 159-166
51EERanganathan Sankaralingam, Nur A. Touba: Inserting Test Points to Control Peak Power During Scan Testing. DFT 2002: 138-146
50EEKedarnath J. Balakrishnan, Nur A. Touba: Matrix-Based Test Vector Decompression Using an Embedded Processor. DFT 2002: 159-165
49EEKartik Mohanram, Nur A. Touba: Input Ordering in Concurrent Checkers to Reduce Power Consumption. DFT 2002: 87-98
48EEKartik Mohanram, C. V. Krishna, Nur A. Touba: A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL. ISCAS (1) 2002: 577-580
47EEC. V. Krishna, Nur A. Touba: Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression. ITC 2002: 321-330
46EERanganathan Sankaralingam, Nur A. Touba: Controlling Peak Power During Scan Testing. VTS 2002: 153-159
45EEEric MacDonald, Nur A. Touba: Very Low Voltage Testing of SOI Integrated Circuits. VTS 2002: 25-30
44EENur A. Touba: Circular BIST with state skipping. IEEE Trans. VLSI Syst. 10(5): 668-672 (2002)
43EEAbhijit Jas, Nur A. Touba: Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor. J. Electronic Testing 18(4-5): 503-514 (2002)
2001
42EEJayabrata Ghosh-Dastidar, Nur A. Touba: Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability. DFT 2001: 215-220
41 C. V. Krishna, Abhijit Jas, Nur A. Touba: Test vector encoding using partial LFSR reseeding. ITC 2001: 885-893
40EEAbhijit Jas, C. V. Krishna, Nur A. Touba: Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme. VTS 2001: 2-8
39EERanganathan Sankaralingam, Nur A. Touba, Bahram Pouya: Reducing Power Dissipation during Test Using Scan Chain Disable. VTS 2001: 319-325
38EENur A. Touba, Edward J. McCluskey: Bit-fixing in pseudorandom sequences for scan BIST. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 545-555 (2001)
2000
37EEEric MacDonald, Nur A. Touba: Testing domino circuits in SOI technology. Asian Test Symposium 2000: 441-446
36EEDebaleena Das, Nur A. Touba, Markus Seuring, Michael Gössel: Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes. IOLTW 2000: 171-
35 Debaleena Das, Nur A. Touba: Reducing test data volume using external/LBIST hybrid test patterns. ITC 2000: 115-122
34EERanganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba: Static Compaction Techniques to Control Scan Vector Power Dissipation. VTS 2000: 35-42
33EEAbhijit Jas, Bahram Pouya, Nur A. Touba: Virtual Scan Chains: A Means for Reducing Scan Length in Cores. VTS 2000: 73-78
32EEJayabrata Ghosh-Dastidar, Nur A. Touba: A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains. VTS 2000: 79-88
1999
31EEAbhijit Jas, Kartik Mohanram, Nur A. Touba: An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. Asian Test Symposium 1999: 275-
30EEAbhijit Jas, Nur A. Touba: Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. ICCD 1999: 418-
29EEP. K. Jaini, Nur A. Touba: Observing test response of embedded cores through surrounding logic. ISCAS (1) 1999: 119-123
28EEW. Quddus, Abhijit Jas, Nur A. Touba: Configuration self-test in FPGA-based reconfigurable systems. ISCAS (1) 1999: 97-100
27 Eric MacDonald, Nur A. Touba: Delay testing of SOI circuits: Challenges with the history effect. ITC 1999: 269-275
26 Jayabrata Ghosh-Dastidar, Debaleena Das, Nur A. Touba: Fault diagnosis in scan-based BIST using both time and space information. ITC 1999: 95-102
25EEDebaleena Das, Nur A. Touba: A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems. VLSI Design 1999: 266-269
24EEAbhijit Jas, Jayabrata Ghosh-Dastidar, Nur A. Touba: Scan Vector Compression/Decompression Using Statistical Coding. VTS 1999: 114-120
23EEJayabrata Ghosh-Dastidar, Nur A. Touba: Adaptive Techniques for Improving Delay Fault Diagnosis. VTS 1999: 168-172
22EEDebaleena Das, Nur A. Touba: Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits. VTS 1999: 370-377
21EENur A. Touba, Edward J. McCluskey: RP-SYN: synthesis of random pattern testable circuits with test point insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 18(8): 1202-1213 (1999)
20EEDebaleena Das, Nur A. Touba: Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes. J. Electronic Testing 15(1-2): 145-155 (1999)
1998
19EEMadhavi Karkala, Nur A. Touba, Hans-Joachim Wunderlich: Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST. Asian Test Symposium 1998: 492-499
18EEJayabrata Ghosh-Dastidar, Nur A. Touba: A Systematic Approach for Diagnosing Multiple Delay Faults. DFT 1998: 211-216
17EEZhe Zhao, Bahram Pouya, Nur A. Touba: BETSY: synthesizing circuits for a specified BIST environment. ITC 1998: 144-153
16EEAbhijit Jas, Nur A. Touba: Test vector decompression via cyclical scan chains and its application to testing core-based designs. ITC 1998: 458-464
15EEDebaleena Das, Nur A. Touba: Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes. VTS 1998: 309-317
14EEBahram Pouya, Nur A. Touba: Synthesis of Zero-Aliasing Elementary-Tree Space Compactors. VTS 1998: 70-77
1997
13 Nur A. Touba, Edward J. McCluskey: Pseudo-Random Pattern Testing of Bridging Faults. ICCD 1997: 54-60
12 Bahram Pouya, Nur A. Touba: Modifying User-Defined Logic for Test Access to Embedded Cores. ITC 1997: 60-68
11EENur A. Touba, Bahram Pouya: Testing Embedded Cores Using Partial Isolation Rings. VTS 1997: 10-16
10EENur A. Touba: Obtaining High Fault Coverage with Circular BIST Via State Skipping. VTS 1997: 410-415
9EENur A. Touba, Bahram Pouya: Using Partial Isolation Rings to Test Core-Based Designs. IEEE Design & Test of Computers 14(4): 52-59 (1997)
8EENur A. Touba, Edward J. McCluskey: Logic synthesis of multilevel circuits with concurrent error detection. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 783-789 (1997)
1996
7 Nur A. Touba, Edward J. McCluskey: Altering a Pseudo-Random Bit Sequence for Scan-Based BIST. ITC 1996: 167-175
6EENur A. Touba, Edward J. McCluskey: Test point insertion based on path tracing. VTS 1996: 2-8
5EENur A. Touba, Edward J. McCluskey: Applying two-pattern tests using scan-mapping. VTS 1996: 393-399
1995
4 Nur A. Touba, Edward J. McCluskey: Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST. ITC 1995: 674-682
3EENur A. Touba, Edward J. McCluskey: Transformed pseudo-random patterns for BIST. VTS 1995: 410-416
1994
2EENur A. Touba, Edward J. McCluskey: Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. ICCAD 1994: 651-654
1 Nur A. Touba, Edward J. McCluskey: Automated Logic Synthesis of Random-Pattern-Testable Circuits. ITC 1994: 174-183

Coauthor Index

1Kedarnath J. Balakrishnan [50] [55] [63] [64] [70] [79] [80] [82] [88]
2Sugato Basu [58] [71] [73] [74] [75]
3Cristiana Bolchini [92]
4Krishnendu Chakrabarty [54]
5Minsu Choi [93]
6Debaleena Das [15] [20] [22] [25] [26] [35] [36]
7Scott Davidson [95]
8Avijit Dutta [76] [84] [86] [89] [91]
9Ritesh Garg [96]
10Shalini Ghosh [58] [71] [73] [74] [75]
11Jayabrata Ghosh-Dastidar [18] [23] [24] [26] [32] [42] [53]
12Michael Gössel [36] [59]
13P. K. Jaini [29]
14Abhijit Jas [16] [24] [28] [30] [31] [33] [40] [41] [43] [53] [65] [66] [68]
15Madhavi Karkala [19]
16Yong-Bin Kim [92]
17C. V. Krishna [40] [41] [47] [48] [60] [62] [66] [68] [69]
18Jinkyu Lee [72] [78] [85] [87]
19Lei Li [54]
20Eric MacDonald [27] [37] [45] [73] [81]
21Edward J. McCluskey [1] [2] [3] [4] [5] [6] [7] [8] [13] [21] [38]
22Kartik Mohanram [31] [48] [49] [56] [57] [59] [61] [67]
23Mom-Eng Ng [53]
24Rama Rao Oruganti [34]
25Srinivas Patil [80]
26Bahram Pouya [9] [11] [12] [14] [17] [33] [39] [65]
27Richard Putman [90] [96]
28W. Quddus [28]
29Terence Rodrigues [76]
30Adelio Salsano [92] [93]
31Ranganathan Sankaralingam [34] [39] [46] [51] [52]
32Chris Schattauer [77]
33Markus Seuring [36]
34Egor S. Sogomonyan [59]
35Samuel I. Ward [77]
36Hans-Joachim Wunderlich [19]
37Joon-Sung Yang [97] [98]
38Zhe Zhao [17]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)