dblp.uni-trier.dewww.uni-trier.de

Parthasarathy P. Tirumalai Vis

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo

*1992
6 Gerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler: Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. ISMVL 1992: 66-74
5EEB. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai: Code generation schema for modulo scheduled loops. MICRO 1992: 158-169
4 B. Ramakrishna Rau, M. Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker: Register Allocation for Software Pipelined Loops. PLDI 1992: 283-299
1991
3 Parthasarathy P. Tirumalai, Varadarajan G. Vadakkencherry: Parallel Algorithms for Minimizing Multiple-Valued Programmable Logic Arrays. ISMVL 1991: 287-295
2 Parthasarathy P. Tirumalai, Jon T. Butler: Minimization Algorithms for Multiple-Valued Programmable Logic Arrays. IEEE Trans. Computers 40(2): 167-177 (1991)
1990
1EEParthasarathy P. Tirumalai, M. Lee, Michael S. Schlansker: Parallelization of loops with exits on pipelined architectures. SC 1990: 200-212

Coauthor Index

1Jon T. Butler [2] [6]
2Gerhard W. Dueck [6]
3Robert C. Earle [6]
4M. Lee [1] [4]
5B. Ramakrishna Rau [4] [5]
6Michael S. Schlansker [1] [4] [5]
7Varadarajan G. Vadakkencherry [3]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)