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Donald E. Thomas Vis

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*2007
65EEBrett H. Meyer, Donald E. Thomas: Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC. CODES+ISSS 2007: 3-8
64EEAlex Bobrek, JoAnn M. Paul, Donald E. Thomas: Event-based re-training of statistical contention models for heterogeneous multiprocessors. CODES+ISSS 2007: 69-74
63EEAlex Bobrek, JoAnn M. Paul, Donald E. Thomas: Shared Resource Access Attributes for High-Level Contention Models. DAC 2007: 720-725
62EEBrett H. Meyer, Donald E. Thomas: Rethinking Automated Synthesis of MPSoC Architectures. IPDPS 2007: 1-6
2006
61EEJoAnn M. Paul, Donald E. Thomas, Alex Bobrek: Scenario-oriented design for single-chip heterogeneous multiprocessors. IEEE Trans. VLSI Syst. 14(8): 868-880 (2006)
2005
60EEJoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy: High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. ACM Trans. Design Autom. Electr. Syst. 10(3): 431-461 (2005)
59EEPhilip Koopman, Howie Choset, Rajeev Gandhi, Bruce H. Krogh, Diana Marculescu, Priya Narasimhan, JoAnn M. Paul, Ragunathan Rajkumar, Daniel P. Siewiorek, Asim Smailagic, Peter Steenkiste, Donald E. Thomas, Chenxi Wang: Undergraduate embedded system education at Carnegie Mellon. ACM Trans. Embedded Comput. Syst. 4(3): 500-528 (2005)
2004
58EEJoAnn M. Paul, Donald E. Thomas, Alex Bobrek: Benchmark-based design strategies for single chip heterogeneous multiprocessors. CODES+ISSS 2004: 54-59
57EEJoshua J. Pieper, Alain Mellan, JoAnn M. Paul, Donald E. Thomas, Faraydon Karim: High level cache simulation for heterogeneous multiprocessors. DAC 2004: 287-292
56EEAlex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, JoAnn M. Paul, Donald E. Thomas: Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach. DATE 2004: 1144-1149
2003
55EEJoAnn M. Paul, Alex Bobrek, Jeffrey E. Nelson, Joshua J. Pieper, Donald E. Thomas: Schedulers as model-based design elements in programmable heterogeneous multiprocessors. DAC 2003: 408-411
54EEAndrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas: Layered, Multi-Threaded, High-Level Performance Design. DATE 2003: 10954-10959
2002
53EEJoAnn M. Paul, Christopher M. Eatedali, Donald E. Thomas: The design context of concurrent computation systems. CODES 2002: 19-24
52EEJoAnn M. Paul, Donald E. Thomas: A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems. DATE 2002: 522-528
51EEJoAnn M. Paul, Arne J. Suppé, Henele I. Adams, Donald E. Thomas: Multi-Level Modeling of Software on Hardware in Concurrent Computation. IPDPS 2002
50EEAndrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul: System-Level Modeling of a Network Switch SoC. ISSS 2002: 62-67
2001
49EENeal K. Tibrewala, JoAnn M. Paul, Donald E. Thomas: Modeling and evaluation of hardware/software designs. CODES 2001: 11-16
48 JoAnn M. Paul, Arne J. Suppé, Donald E. Thomas: Modeling and simulation of steady state and transient behaviors for emergent SoCs. ISSS 2001: 262-267
47EESandra J. Weber, JoAnn M. Paul, Donald E. Thomas: Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device. IEEE Trans. VLSI Syst. 9(6): 805-812 (2001)
2000
46EEJoAnn M. Paul, Simon N. Peffers, Donald E. Thomas: Frequency interleaving as a codesign scheduling paradigm. CODES 2000: 131-135
45EEJoAnn M. Paul, Simon N. Peffers, Donald E. Thomas: A codesign virtual machine for hierarchical, balanced hardware/software system modeling. DAC 2000: 390-395
44EEWilliam E. Dougherty, Donald E. Thomas: Unifying behavioral synthesis and physical design. DAC 2000: 756-761
43EESari L. Coumeri, Donald E. Thomas: Memory modeling for system synthesis. IEEE Trans. VLSI Syst. 8(3): 327-334 (2000)
1999
42EEDonald E. Thomas, JoAnn M. Paul, Simon N. Peffers, Sandra J. Weber: Peer-based multithreaded executable co-specification. CODES 1999: 105-109
41EEChristopher Inacio, Herman Schmit, David Nagle, Andrew Ryan, Donald E. Thomas, Yingfai Tong, Ben Klass: Vertical Benchmarks for CAD. DAC 1999: 408-413
40EESari L. Coumeri, Donald E. Thomas: An Environment for Exploring Low Power Memory Configurations in System Level Design. ICCD 1999: 348-353
39EEWilliam E. Dougherty, Donald E. Thomas: Modeling and automating selection of guarding techniques for datapath elements. ISLPED 1999: 182-187
38EEWilliam E. Dougherty, David J. Pursley, Donald E. Thomas: Subsetting Behavioral Intellectual Property for Low Power ASIP Design. VLSI Signal Processing 21(3): 209-218 (1999)
1998
37EESrihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, Donald E. Thomas: Managing Pipeline-Reconfigurable FPGAs. FPGA 1998: 55-64
36EESari L. Coumeri, Donald E. Thomas: Memory modeling for system synthesis. ISLPED 1998: 179-184
35EEHerman Schmit, Donald E. Thomas: Address generation for memories containing multiple arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 377-385 (1998)
1997
34EEHerman Schmit, Donald E. Thomas: Synthesis of application-specific memory designs. IEEE Trans. VLSI Syst. 5(1): 101-111 (1997)
1996
33EEJay K. Adams, Donald E. Thomas: The Design of Mixed Hardware/Software Systems. DAC 1996: 515-520
1995
32EEPrashant Sawkar, Donald E. Thomas: Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs. DAC 1995: 201-205
31EEHerman Schmit, Donald E. Thomas: Hidden Markov modeling and fuzzy controllers in FPGAs. FCCM 1995: 214-221
30EEHerman Schmit, Donald E. Thomas: Address generation for memories containing multiple arrays. ICCAD 1995: 510-514
29EEJay K. Adams, John Alan Miller, Donald E. Thomas: Execution-time profiling for multiple-process behavioral synthesis. ICCD 1995: 144-149
28EEJay K. Adams, Donald E. Thomas: Multiple-process behavioral synthesis for mixed hardware-software systems. ISSS 1995: 10-15
27EEHerman Schmit, Donald E. Thomas: Array mapping in behavioral synthesis. ISSS 1995: 90-95
1994
26EELawrence F. Arnstein, Donald E. Thomas: The Attributed-Behavior Abstraction and Synthesis Tools. DAC 1994: 557-561
25 R. S. Ramchandani, Donald E. Thomas: Behavioral-Test Generation using Mixed-Integer Non-linear Programming. ITC 1994: 958-967
24EED. L. Springer, Donald E. Thomas: Exploiting the special structure of conflict and compatibility graphs in high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 13(7): 843-856 (1994)
1993
23EEPrashant Sawkar, Donald E. Thomas: Performance Directed Technology Mapping for Look-Up Table Based FPGAs. DAC 1993: 208-212
22EERichard J. Cloutier, Donald E. Thomas: Synthesis of Pipelined Instruction Set Processors. DAC 1993: 583-588
21EELawrence F. Arnstein, Donald E. Thomas: A general consistency technique for increasing the controllability of high level synthesis tools. ICCAD 1993: 741-744
20EEDonald E. Thomas, Jay K. Adams, Herman Schmit: A Model and Methodology for Hardware-Software Codesign. IEEE Design & Test of Computers 10(3): 6-15 (1993)
1992
19EEPrashant Sawkar, Donald E. Thomas: Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate Arrays. DAC 1992: 368-373
18 Jay K. Adams, Donald E. Thomas: Addressing the Tradeoff Between Standard and Custom ICs in System Level Design. ICCD 1992: 194-197
1991
17EEElizabeth D. Lagnese, Donald E. Thomas: Architectural partitioning for system level synthesis of integrated circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(7): 847-860 (1991)
1990
16EERichard J. Cloutier, Donald E. Thomas: The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm. DAC 1990: 71-76
15 D. L. Springer, Donald E. Thomas: Exploiting the Special Structure of Conflict and Compatibility Graphs in High-Level Synthesis. ICCAD 1990: 254-257
1989
14EEElizabeth D. Lagnese, Donald E. Thomas: Architectural Partitioning for System Level Design. DAC 1989: 62-67
13EERobert A. Walker, Donald E. Thomas: Behavioral transformation for algorithmic level IC design. IEEE Trans. on CAD of Integrated Circuits and Systems 8(10): 1115-1128 (1989)
1988
12EEDonald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn: The System Architect's Workbench. DAC 1988: 337-343
11EERobert L. Blackburn, Donald E. Thomas, Patti M. Koenig: CORAL II: Linking Behavior and Structure in an IC Design System. DAC 1988: 529-535
1987
10EEDonald E. Thomas, Robert L. Blackburn, Jayanth V. Rajan: Linking the Behavioral and Structural Domains of Representation for Digital System Design. IEEE Trans. on CAD of Integrated Circuits and Systems 6(1): 103-110 (1987)
1985
9EEDonald E. Thomas: Observations on comparing digital systems synthesis techniques. ACM Conference on Computer Science 1985: 17-22
8EEThaddeus J. Kowalski, Donald E. Thomas: The VLSI design automation assistant: what's in a knowledge base. DAC 1985: 252-258
7EEJayanth V. Rajan, Donald E. Thomas: Synthesis by delayed binding of decisions. DAC 1985: 367-373
6EERobert L. Blackburn, Donald E. Thomas: Linking the behavioral and structural dominis of representation in a synthesis system. DAC 1985: 374-380
5EERobert A. Walker, Donald E. Thomas: A model of design representation and synthesis. DAC 1985: 453-459
1983
4 Donald E. Thomas, Charles Y. Hitchcock III, Thaddeus J. Kowalski, Jayanth V. Rajan, Robert A. Walker: Automatic Data Path Synthesis. IEEE Computer 16(12): 59-70 (1983)
3EEDonald E. Thomas, G. W. Leive: Automating Technology Relative Logic Synthesis and Module Selection. IEEE Trans. on CAD of Integrated Circuits and Systems 2(2): 94-105 (1983)
2EEDonald E. Thomas, John A. Nestor: Defining and Implementing a Multilevel Design Representation with Simulation Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 2(3): 135-145 (1983)
1981
1 Donald E. Thomas, Daniel P. Siewiorek: Measuring Designer Performance to Verify Design Automation Systems. IEEE Trans. Computers 30(1): 48-61 (1981)

Coauthor Index

1Henele I. Adams [51]
2Jay K. Adams [18] [20] [28] [29] [33]
3Christopher P. Andrews [50]
4Lawrence F. Arnstein [21] [26]
5Robert L. Blackburn [6] [10] [11] [12]
6Alex Bobrek [55] [56] [58] [61] [63] [64]
7Srihari Cadambi [37]
8Andrew S. Cassidy [50] [54] [60]
9Howie Choset [59]
10Richard J. Cloutier [16] [22]
11Sari L. Coumeri [36] [40] [43]
12Elizabeth M. Dirkes [12]
13William E. Dougherty [38] [39] [44]
14Christopher M. Eatedali [53]
15Rajeev Gandhi [59]
16Seth Copen Goldstein [37]
17Charles Y. Hitchcock III [4]
18Christopher Inacio [41]
19Faraydon Karim [57]
20Ben Klass [41]
21Patti M. Koenig [11]
22Philip Koopman (Phil Koopman, Philip J. Koopman Jr.) [59]
23Thaddeus J. Kowalski [4] [8]
24Bruce H. Krogh [59]
25Elizabeth D. Lagnese [14] [17]
26G. W. Leive [3]
27Diana Marculescu [59]
28Alain Mellan [57]
29Brett H. Meyer [62] [65]
30John Alan Miller [29]
31David Nagle [41]
32Priya Narasimhan [59]
33Jeffrey E. Nelson [55] [56]
34John A. Nestor [2] [12]
35JoAnn M. Paul [42] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] [59] [60] [61] [63] [64]
36Simon N. Peffers [42] [45] [46]
37Joshua J. Pieper [55] [56] [57]
38David J. Pursley [38]
39Jayanth V. Rajan [4] [7] [10] [12]
40Ragunathan Rajkumar [59]
41R. S. Ramchandani [25]
42Andrew Ryan [41]
43Prashant Sawkar [19] [23] [32]
44Herman Schmit [20] [27] [30] [31] [34] [35] [37] [41]
45Daniel P. Siewiorek [1] [59]
46Asim Smailagic [59]
47D. L. Springer [15] [24]
48Peter Steenkiste [59]
49Arne J. Suppé [48] [51]
50Neal K. Tibrewala [49]
51Yingfai Tong [41]
52Robert A. Walker [4] [5] [12] [13]
53Chenxi Wang [59]
54Sandra J. Weber [42] [47]
55Jeffrey Weener [37]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)