Alexander Thomas

2007
13	EE	Alexander Thomas, Jürgen Becker: New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur). it - Information Technology 49(3): 165- (2007)
2006
12	EE	Alexander Thomas, Vittorio Ferrari, Bastian Leibe, Tinne Tuytelaars, Bernt Schiele, Luc J. Van Gool: Towards Multi-View Object Class Detection. CVPR (2) 2006: 1589-1596
2005
11		Alexander Thomas: Design of a Dynamic Reconfigurable Multi-Grained Hardware Architecture with Adaptive Runtime Routing. FPL 2005: 745-746
10	EE	Alexander Thomas, Jürgen Becker: Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures. ISVLSI 2005: 118-123
9		Jürgen Becker, Michael Hübner, Katarina Paulsson, Alexander Thomas: Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics. ReCoSoC 2005: 35-42
8	EE	Jürgen Becker, Alexander Thomas: Scalable Processor Instruction Set Extension. IEEE Design & Test of Computers 22(2): 136-148 (2005)
2004
7		Alexander Thomas, Jürgen Becker: Aufbau- und Strukturkonzepte einer adaptive multigranularen rekonfigurierbaren Hardwarearchitektur. ARCS Workshops 2004: 165-174
6	EE	Alexander Thomas, Jürgen Becker: Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures. FPL 2004: 115-124
5	EE	Alexander Thomas, Thomas Zander, Jürgen Becker: Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures. SBCCI 2004: 141-146
2003
4	EE	Jürgen Becker, Alexander Thomas, Martin Vorbach, Volker Baumgarten: An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration. DATE 2003: 11120-11121
3	EE	Jens E. Becker, Carsten Bieser, Alexander Thomas, Klaus D. Müller-Glaser, Jürgen Becker: Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core. MSE 2003: 134-135
2	EE	Jürgen Becker, Alexander Thomas, Maik Scheer: Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration. SBCCI 2003: 237-242
1		Jürgen Becker, Alexander Thomas, Maik Scheer: Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processors. VLSI-SOC 2003: 288-

Coauthor Index

1	Volker Baumgarten	[4]
2	Jens E. Becker	[3]
3	Jürgen Becker	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [13]
4	Carsten Bieser	[3]
5	Vittorio Ferrari	[12]
6	Luc J. Van Gool	[12]
7	Michael Hübner	[9]
8	Bastian Leibe	[12]
9	Klaus D. Müller-Glaser	[3]
10	Katarina Paulsson	[9]
11	Maik Scheer	[1] [2]
12	Bernt Schiele	[12]
13	Tinne Tuytelaars	[12]
14	Martin Vorbach	[4]
15	Thomas Zander	[5]

Colors in the list of coauthors