dblp.uni-trier.dewww.uni-trier.de

Paul J. Thadikaran Vis

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo

*2009
16EEGoutam Debnath, Paul J. Thadikaran: Design for Manufacturability and Reliability in Nano Era. VLSI Design 2009: 33-34
2006
15EEGoutam Debnath, Paul J. Thadikaran: Design Challenges for High Performance Nano-Technology. VLSI Design 2006: 12-13
14EEYu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman: Extraction error modeling and automated model debugging in high-performance custom designs. IEEE Trans. VLSI Syst. 14(7): 763-776 (2006)
2005
13EEYu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman: Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. DATE 2005: 996-1001
12EEXiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran: Efficient techniques for transition testing. ACM Trans. Design Autom. Electr. Syst. 10(2): 258-278 (2005)
2004
11EEDebashis Nayak, Srikanth Venkataraman, Paul J. Thadikaran: Razor: A Tool for Post-Silicon Scan ATPG Pattern Debug and Its Application. VTS 2004: 97-102
2003
10EEYu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris: Extraction Error Diagnosis and Correction in High-Performance Designs. ITC 2003: 423-430
9EEYu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris: Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs. MTV 2003: 54-59
8EEXiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran: Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors. J. Electronic Testing 19(4): 437-445 (2003)
2002
7EEXiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran: Techniques to Reduce Data Volume and Application Time for Transition Test. ITC 2002: 983-992
1997
6EEPaul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel: Algorithms to compute bridging fault coverage of IDDQ test sets. ACM Trans. Design Autom. Electr. Syst. 2(3): 281-305 (1997)
1996
5EEPaul J. Thadikaran, Sreejit Chakravarty: Fast Algorithms for Computer IDDQ Tests for Combination Circuits. VLSI Design 1996: 103-106
4 Sreejit Chakravarty, Paul J. Thadikaran: Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits. IEEE Trans. Computers 45(10): 1131-1140 (1996)
3EESreejit Chakravarty, Paul J. Thadikaran: Algorithms to select IDDQ measurement points to detect bridging faults. J. Electronic Testing 8(3): 275-285 (1996)
1995
2 Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel: Fault Simulation ofIDDQ Tests for Bridging Faults in Sequential Circuits. FTCS 1995: 340-349
1994
1 Sreejit Chakravarty, Paul J. Thadikaran: A Study of IDDQ Subset Selection Algorithms for Bridging Faults. ITC 1994: 403-412

Coauthor Index

1Sreejit Chakravarty [1] [2] [3] [4] [5] [6] [7] [8] [12]
2Goutam Debnath [15] [16]
3Michael S. Hsiao [7] [8] [12]
4Jiang Brandon Liu [9] [10]
5Xiao Liu [7] [8] [12]
6Debashis Nayak [11]
7Janak H. Patel [2] [6]
8Andreas G. Veneris [9] [10] [13] [14]
9Srikanth Venkataraman [11] [13] [14]
10Yu-Shen Yang [9] [10] [13] [14]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)