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Russell Tessier Vis

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*2009
48EESailaja Madduri, Ramakrishna Vadlamani, Wayne Burleson, Russell Tessier: A monitor interconnect and support subsystem for multicore processors. DATE 2009: 761-766
47EEDeming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger: CMOS vs Nano: comrades or rivals? FPGA 2009: 121-122
46EERomain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Eduardo Wanderley Netto, Russell Tessier, Wayne P. Burleson: A security approach for off-chip memory in embedded microprocessor systems. Microprocessors and Microsystems - Embedded Hardware Design 33(1): 37-45 (2009)
45EEWeifeng Xu, Russell Tessier: Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors. TACO 6(3): (2009)
2007
44 Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Wayne Burleson: High-efficiency protection solution for off-chip memory in embedded systems. ERSA 2007: 117-123
43EEThomas Eisenbarth, Tim Güneysu, Christof Paar, Ahmad-Reza Sadeghi, Marko Wolf, Russell Tessier: Establishing Chain of Trust in Reconfigurable Hardware. FCCM 2007: 289-290
42EEKevin Oo Tinmaung, David Howland, Russell Tessier: Power-aware FPGA logic synthesis using binary decision diagrams. FPGA 2007: 148-155
41EEWeifeng Xu, Russell Tessier: Tetris: a new register pressure control technique for VLIW processors. LCTES 2007: 113-122
40 Romain Vaslin, Guy Gogniat, Eduardo Wanderley Netto, Russell Tessier, Wayne P. Burleson: Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory. ReCoSoC 2007: 146-153
39EEIan Kuon, Russell Tessier, Jonathan Rose: FPGA Architecture: Survey and Challenges. Foundations and Trends in Electronic Design Automation 2(2): 135-253 (2007)
38EERussell Tessier, Vaughn Betz, David Neto, Aaron Egier, Thiagaraja Gopalsamy: Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 278-290 (2007)
2006
37EELilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier: An adaptive Reed-Solomon errors-and-erasures decoder. FPGA 2006: 150-158
36EERussell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy: Power-aware RAM mapping for FPGA embedded memory blocks. FPGA 2006: 189-198
35EEPremachandran R. Menon, Weifeng Xu, Russell Tessier: Design-specific path delay testing in lookup-table-based FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 867-877 (2006)
2005
34EERussell Tessier, David Jasinski, Atul Maheshwari, Aiyappan Natarajan, Weifeng Xu, Wayne P. Burleson: An energy-aware active smart card. IEEE Trans. VLSI Syst. 13(10): 1190-1199 (2005)
33EERussell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne P. Burleson: A reconfigurable, power-efficient adaptive Viterbi decoder. IEEE Trans. VLSI Syst. 13(4): 484-488 (2005)
2004
32 Russell Tessier, Herman Schmit: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004 ACM 2004
31EEJian Liang, Russell Tessier, Dennis Goeckel: A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder. FCCM 2004: 91-100
30 Atul Maheshwari, Wayne Burleson, Russell Tessier: Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. IEEE Trans. VLSI Syst. 12(3): 299-311 (2004)
29EEJian Liang, Andrew Laffely, S. Srinivasan, Russell Tessier: An architecture and compiler for scalable on-chip communication. IEEE Trans. VLSI Syst. 12(7): 711-726 (2004)
28EEPrashant Jain, Andrew Laffely, Wayne Burleson, Russell Tessier, Dennis Goeckel: Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations. VLSI Signal Processing 36(1): 27-40 (2004)
27EERoger Woods, Russell Tessier: Guest Editorial: Field Programmable Logic. VLSI Signal Processing 36(1): 5-6 (2004)
2003
26EEAiyappan Natarajan, David Jasinski, Wayne Burleson, Russell Tessier: A hybrid adiabatic content addressable memory for ultra low-power applications. ACM Great Lakes Symposium on VLSI 2003: 72-75
25EEWeifeng Xu, Ramshankar Ramanarayanan, Russell Tessier: Adaptive Fault Recovery for Networked Reconfigurable Systems. FCCM 2003: 143-
24EEJian Liang, Russell Tessier, Oskar Mencer: Floating Point Unit Generation and Evaluation for FPGAs. FCCM 2003: 185-194
23 Andrew Laffely, Jian Liang, Russell Tessier, Wayne Burleson: Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores. ICIP (3) 2003: 105-108
22EESrini Krishnamoorthy, Russell Tessier: Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 545-559 (2003)
2002
21EESriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne Burleson: A dynamically reconfigurable adaptive viterbi decoder. FPGA 2002: 227-236
20EERamaswamy Ramaswamy, Russell Tessier: The Integration of SystemC and Hardware-Assisted Verification. FPL 2002: 1007-1016
19EEAtul Maheshwari, Wayne Burleson, Russell Tessier: Trading off Reliability and Power-Consumption in Ultra-low Power Systems. ISQED 2002: 361-366
18EERussell Tessier: Fast placement approaches for FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(2): 284-305 (2002)
17EENavin Vemuri, Priyank Kalla, Russell Tessier: BDD-based logic synthesis for LUT-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4): 501-525 (2002)
16EEMurali Kudlugi, Russell Tessier: Static scheduling of multidomain circuits for fast functional verification. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1253-1268 (2002)
15EEIan G. Harris, Russell Tessier: Testing and diagnosis of interconnect faults in cluster-based FPGA architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1337-1343 (2002)
2001
14EEMurali Kudlugi, Charles Selvidge, Russell Tessier: Static Scheduling of Multiple Asynchronous Domains For Functional Verification. DAC 2001: 647-652
13EEMurali Kudlugi, Charles Selvidge, Russell Tessier: Static Scheduling of Multi-Domain Memories For Functional Verification. ICCAD 2001: 2-9
12 Ian G. Harris, Premachandran R. Menon, Russell Tessier: BIST-based delay path testing in FPGA architectures. ITC 2001: 932-938
11EERussell Tessier, Wayne Burleson: Reconfigurable Computing for Digital Signal Processing: A Survey. VLSI Signal Processing 28(1-2): 7-27 (2001)
2000
10EEIan G. Harris, Russell Tessier: Interconnect testing in cluster-based FPGA architectures. DAC 2000: 49-54
9EEVijay Lakamraju, Russell Tessier: Tolerating operational faults in cluster-based FPGAs. FPGA 2000: 187-194
8EESrini Krishnamoorthy, Sriram Swaminathan, Russell Tessier: Area-Optimized Technology Mapping for Hybrid FPGAs. FPL 2000: 181-190
7EERussell Tessier, Heather Giza: Balancing Logic Utilization and Area Efficiency in FPGAs. FPL 2000: 535-544
6 Ian G. Harris, Russell Tessier: Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures. ICCAD 2000: 472-475
5EEJian Liang, Sriram Swaminathan, Russell Tessier: aSOC: A Scalable, Single-Chip Communications Architecture. IEEE PACT 2000: 37-46
1999
4EERussell Tessier: Incremental Compilation for Logic Emulation. IEEE International Workshop on Rapid System Prototyping 1999: 236-241
3 Russell Tessier: Frontier: A Fast Placement System for FPGAs. VLSI 1999: 125-136
1997
2EEJonathan Babb, Russell Tessier, Matthew Dahl, Silvina Hanono, David M. Hoki, Anant Agarwal: Logic emulation with virtual wires. IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 609-626 (1997)
1993
1EESteve Ward, Karim Abdalla, Rajeev Dujari, Michael Fetterman, Frank Honoré, Ricardo Jenez, Philippe Laffont, Kenneth Mackenzie, Chris Metcalf, Milan Minsky, John Nguyen, John Pezaris, Gill A. Pratt, Russell Tessier: The NuMesh: A Modular, Scalable Communications Substrate. International Conference on Supercomputing 1993: 230-239

Coauthor Index

1Karim Abdalla [1]
2Anant Agarwal [2]
3Jonathan Allen [37]
4Lilian Atieno [37]
5Jonathan Babb [2]
6Kaustav Banerjee [47]
7Vaughn Betz [36] [38]
8Wayne P. Burleson (Wayne Burleson) [11] [19] [21] [23] [26] [28] [30] [33] [34] [40] [44] [46] [48]
9Deming Chen [47]
10Mojy C. Chian [47]
11Matthew Dahl [2]
12André DeHon [47]
13Jean-Philippe Diguet [44] [46]
14Rajeev Dujari [1]
15Aaron Egier [38]
16Thomas Eisenbarth [43]
17Michael Fetterman [1]
18Shinobu Fujita [47]
19Heather Giza [7]
20Dennis Goeckel [21] [28] [31] [33] [37]
21Guy Gogniat [40] [44] [46]
22Thiagaraja Gopalsamy [36] [38]
23Tim Güneysu [43]
24Silvina Hanono [2]
25Ian G. Harris [6] [10] [12] [15]
26David M. Hoki [2]
27Frank Honoré [1]
28David Howland [42]
29James Hutchby [47]
30Prashant Jain [28]
31David Jasinski [26] [34]
32Ricardo Jenez [1]
33Priyank Kalla [17]
34Srini Krishnamoorthy [8] [22]
35Murali Kudlugi [13] [14] [16]
36Ian Kuon [39]
37Andrew Laffely [23] [28] [29]
38Philippe Laffont [1]
39Vijay Lakamraju [9]
40Jian Liang [5] [23] [24] [29] [31]
41Kenneth Mackenzie [1]
42Sailaja Madduri [48]
43Atul Maheshwari [19] [30] [34]
44Oskar Mencer [24]
45Premachandran R. Menon [12] [35]
46Chris Metcalf [1]
47Milan Minsky [1]
48Aiyappan Natarajan [26] [34]
49David Neto [36] [38]
50Eduardo Wanderley Netto [40] [46]
51John Nguyen [1]
52Christof Paar [43]
53John Pezaris [1]
54Gill A. Pratt [1]
55Ramshankar Ramanarayanan [25]
56Ramaswamy Ramaswamy [20] [33]
57Jonathan Rose [39]
58Ahmad-Reza Sadeghi [43]
59Herman Schmit [32]
60Charles Selvidge [13] [14]
61S. Srinivasan [29]
62Sriram Swaminathan [5] [8] [21] [33]
63Kevin Oo Tinmaung [42]
64Steve Trimberger [47]
65Ramakrishna Vadlamani [48]
66Romain Vaslin [40] [44] [46]
67Navin Vemuri [17]
68Steve Ward [1]
69Marko Wolf [43]
70Roger Woods (Roger F. Woods) [27]
71Weifeng Xu [25] [34] [35] [41] [45]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)