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Jürgen Teich Vis

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*2009
186EEFrank Hannig, Hritam Dutta, Jürgen Teich: Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. ARCS 2009: 16-27
185EEHritam Dutta, Frank Hannig, Jürgen Teich: Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. ARCS 2009: 233-245
184EEHritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich: Impact of Loop Tiling on the Controller Logic of Acceleration Engines. ASAP 2009: 161-168
183EERichard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, Jürgen Teich: Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. ASAP 2009: 211-214
182EEMartin Lukasiewycz, Michael Glaß, Jürgen Teich: Exploiting data-redundancy in reliability-aware networked embedded system design. CODES+ISSS 2009: 229-238
181EEMartin Lukasiewycz, Michael Glaß, Jürgen Teich, Paul Milbredt: FlexRay schedule optimization of the static segment. CODES+ISSS 2009: 363-372
180EEMichael Glaß, Martin Lukasiewycz, Jürgen Teich, Unmesh D. Bordoloi, Samarjit Chakraborty: Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis. DAC 2009: 43-46
179EETobias Ziermann, Stefan Wildermann, Jürgen Teich: CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates. DATE 2009: 1088-1093
178EEJoachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich: Model-based synthesis and optimization of static multi-rate image processing algorithms. DATE 2009: 135-140
177EEMichael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich: Incorporating graceful degradation into embedded system design. DATE 2009: 320-323
176EEMartin Lukasiewycz, Martin Streubühr, Michael Glaß, Christian Haubelt, Jürgen Teich: Combined system synthesis and communication architecture exploration for MPSoCs. DATE 2009: 472-477
175EEDirk Koch, Christian Beckhoff, Jürgen Teich: A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs. FPGA 2009: 253-256
174EERichard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich: Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. SAMOS 2009: 277-288
173EEJoachim Keinert, Martin Streubühr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt, Jürgen Teich, Michael Meredith: SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications. ACM Trans. Design Autom. Electr. Syst. 14(1): (2009)
172EEHritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier: A holistic approach for tightly coupled reconfigurable parallel processors. Microprocessors and Microsystems - Embedded Hardware Design 33(1): 53-62 (2009)
171EEDirk Koch, Christian Beckhoff, Jürgen Teich: Hardware Decompression Techniques for FPGA-Based Embedded Systems. TRETS 2(2): (2009)
2008
170EEJosef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele: Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. ARC 2008: 148-158
169EEFrank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich: PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. ARC 2008: 284-289
168EERobert Brendle, Thilo Streichert, Dirk Koch, Christian Haubelt, Jürgen Teich: Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks. ARCS 2008: 117-129
167EEJoachim Keinert, Christian Haubelt, Jürgen Teich: Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order Communication. ARCS 2008: 130-143
166EEThilo Streichert, Michael Glaß, Rolf Wanka, Christian Haubelt, Jürgen Teich: Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks. ARCS 2008: 23-37
165EEMartin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich: Efficient symbolic multi-objective design space exploration. ASP-DAC 2008: 691-696
164EEDaniel Ziener, Jürgen Teich: Concepts for Autonomous Control Flow Checking for Embedded CPUs. ATC 2008: 234-248
163EEFelix Reimann, Michael Glabeta, Martin Lukasiewycz, Joachim Keinert, Christian Haubelt, Jürgen Teich: Symbolic voter placement for dependability-aware system synthesis. CODES+ISSS 2008: 237-242
162EEMartin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, Richard Regler, Bardo Lang: Concurrent topology and routing optimization in automotive network integration. DAC 2008: 626-629
161EEMichael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich: Symbolic Reliability Analysis and Optimization of ECU Networks. DATE 2008: 158-163
160EEChristophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. DSD 2008: 345-352
159EERainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich: Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. DSD 2008: 391-398
158EEJoachim Falk, Joachim Keinert, Christian Haubelt, Jürgen Teich, Shuvra S. Bhattacharyya: A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications. EMSOFT 2008: 189-198
157EEDirk Koch, Christian Haubelt, Jürgen Teich: Efficient Reconfigurable On-Chip Buses for FPGAs. FCCM 2008: 287-290
156EEChristophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. FCCM 2008: 306-309
155EEJens Gladigau, Christian Haubelt, Jürgen Teich: Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models. FDL 2008: 1-6
154EESándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich: No-break dynamic defragmentation of reconfigurable devices. FPL 2008: 113-118
153EEDirk Koch, Christian Beckhoff, Jürgen Teich: ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS. FPL 2008: 119-124
152EEJosef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, T. Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker: Fine grain reconfigurable architectures. FPL 2008: 348
151EESven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner: Coarse-grained reconfiguration. FPL 2008: 349
150EEChristophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. FPL 2008: 391-396
149EEChristopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich: A comparison of embedded reconfigurable video-processing architectures. FPL 2008: 587-590
148EEMartin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich: A feasibility-preserving local search operator for constrained discrete optimization problems. IEEE Congress on Evolutionary Computation 2008: 1968-1975
147EEJosef Angermeier, Jürgen Teich: Heuristics for scheduling reconfigurable devices with consideration of reconfiguration overheads. IPDPS 2008: 1-8
146EEChristian Zebelein, Joachim Falk, Christian Haubelt, Jürgen Teich: Classification of General Data Flow Actors into Known Models of Computation. MEMOCODE 2008: 119-128
145EEDmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich: Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. PATMOS 2008: 307-317
144EEMartin Lukasiewycz, Michael Glaß, Jürgen Teich: A Feasibility-Preserving Crossover and Mutation Operator for Constrained Combinatorial Problems. PPSN 2008: 919-928
143EEStefan Wildermann, Jürgen Teich: 3D Person Tracking with a Color-Based Particle Filter. RobVis 2008: 327-340
142EEMichael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich: Symbolic Reliability Analysis of Self-healing Networked Embedded Systems. SAFECOMP 2008: 139-152
141EESándor P. Fekete, Jan van der Veen, Ali Ahmadinia, Diana Göhringer, Mateusz Majer, Jürgen Teich: Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device. IEEE Trans. VLSI Syst. 16(9): 1210-1219 (2008)
140EEDaniel Ziener, Jürgen Teich: Power Signature Watermarking of IP Cores for FPGAs. Signal Processing Systems 51(1): 123-136 (2008)
139 Jürgen Teich: Invasive Algorithms and Architectures (Invasive Algorithmen und Architekturen). it - Information Technology 50(5): 300-310 (2008)
2007
138 Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt, Jürgen Teich: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007 ACM 2007
137EEAlexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement: Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS 2007: 268-282
136EEMichael Glaß, Martin Lukasiewycz, Thilo Streichert, Christian Haubelt, Jürgen Teich: Interactive presentation: Reliability-aware system synthesis. DATE 2007: 409-414
135 Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet: A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA 2007: 14-24
134EEJoachim Keinert, Joachim Falk, Christian Haubelt, Jürgen Teich: Actor-Oriented Modeling and Simulation of Sliding Window Image Processing Algorithms. ESTImedia 2007: 113-118
133EEJens Gladigau, Christian Haubelt, Bernhard Niemann, Jürgen Teich: Mapping Actor-Oriented Models to TLM Architectures. FDL 2007: 128-133
132EEDirk Koch, Christian Haubelt, Jürgen Teich: Efficient hardware checkpointing: concepts, overhead analysis, and implementation. FPGA 2007: 188-196
131EEJoachim Keinert, Christian Haubelt, Jürgen Teich: Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow. ICSAMOS 2007: 161-168
130EEMartin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich: SAT-decoding in evolutionary algorithms for discrete constrained optimization problems. IEEE Congress on Evolutionary Computation 2007: 935-942
129EEDirk Koch, Christian Haubelt, Thilo Streichert, Jürgen Teich: Modeling and Synthesis of Hardware-Software Morphing. ISCAS 2007: 2746-2749
128 Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier: Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68
127EEMartin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich: Solving Multi-objective Pseudo-Boolean Problems. SAT 2007: 56-69
126EEAlexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich: Efficient event-driven simulation of parallel processor architectures. SCOPES 2007: 71-80
125EEThilo Streichert, Michael Glaß, Christian Haubelt, Jürgen Teich: Design space exploration of reliable networked embedded systems. Journal of Systems Architecture 53(10): 751-763 (2007)
124EEHritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich: Efficient control generation for mapping nested loop programs onto processor arrays. Journal of Systems Architecture 53(5-6): 300-309 (2007)
123EEMateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda: The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer. VLSI Signal Processing 47(1): 15-31 (2007)
122EEJürgen Teich: Reconfigurable Computing Systems (Rekonfigurierbare Rechensysteme). it - Information Technology 49(3): 139- (2007)
121EEJosef Angermeier, Diana Göhringer, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens). it - Information Technology 49(3): 143- (2007)
2006
120 Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich: Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006 Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany 2006
119EEHritam Dutta, Frank Hannig, Jürgen Teich: Controller Synthesis for Mapping Partitioned Programs on Array Architectures. ARCS 2006: 176-190
118EEDirk Koch, Thilo Streichert, Steffen Dittrich, Christian Strengert, Christian Haubelt, Jürgen Teich: An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks. ARCS 2006: 202-216
117 Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich: A Flexible Reconfiguration Manager for the Erlangen Slot Machine. ARCS Workshops 2006: 183-194
116EEHritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger: A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. ASAP 2006: 331-340
115 Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich: A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES 2006: 189-195
114EEJürgen Teich: Are current ESL tools meeting the requirements of advanced embedded systems? CODES+ISSS 2006: 166
113EEMartin Streubühr, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch, Thomas Schlipf: Task-accurate performance modeling in SystemC for real-time multi-processor architectures. DATE 2006: 480-481
112EEJürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas: 06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006
111EEJürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas: 06141 Executive Summary -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006
110EEDiana Göhringer, Mateusz Majer, Jürgen Teich: Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine. Dynamically Reconfigurable Architectures 2006
109EEMartin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich: Symbolic Archive Representation for a Fast Nondominance Test. EMO 2006: 111-125
108 Dirk Koch, Matthiaas Koerber, Jürgen Teich: Searching RC5-Keys with Distributed Reconfigurable Computing. ERSA 2006: 42-48
107EEJürgen Teich, Stefanos Kaxiras, Toomas P. Plaks, Krisztián Flautner: Topic 18: Embedded Parallel Systems. Euro-Par 2006: 1179
106EEJoachim Falk, Christian Haubelt, Jürgen Teich: Efficient Representation and Simulation of Model-Based Designs. FDL 2006: 129-135
105EEDaniel Ziener, Stefan Assmus, Jürgen Teich: Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. FPL 2006: 1-6
104EESándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich: Minimizing Communication Cost for Reconfigurable Slot Modules. FPL 2006: 1-6
103EEThilo Streichert, Christian Haubelt, Jürgen Teich: Multi-Objective Topology Optimization for Networked Embedded Systems. ICSAMOS 2006: 93-98
102EEThomas Schlichter, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich: Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms. ISVLSI 2006: 309-316
101EEHritam Dutta, Frank Hannig, Jürgen Teich: Hierarchical Partitioning for Piecewise Linear Algorithms. PARELEC 2006: 153-160
100 Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich: A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. ReCoSoC 2006: 31-37
99EEThilo Streichert, Christian Strengert, Christian Haubelt, Jürgen Teich: Dynamic task binding for hardware/software reconfigurable networks. SBCCI 2006: 38-43
98EEFrank Hannig, Hritam Dutta, Jürgen Teich: Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology. IJES 2(1/2): 114-127 (2006)
97EESándor P. Fekete, Ekkehard Köhler, Jürgen Teich: Higher-Dimensional Packing with Order Constraints. SIAM J. Discrete Math. 20(4): 1056-1078 (2006)
96EEJürgen Teich, Shuvra S. Bhattacharyya: Analysis of Dataflow Programs with Interval-limited Data-rates. VLSI Signal Processing 43(2-3): 247-258 (2006)
2005
95EEThomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich: Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. ASAP 2005: 9-14
94EEChristian Haubelt, Stephan Otto, Cornelia Grabbe, Jürgen Teich: A system-level approach to hardware reconfigurable systems. ASP-DAC 2005: 298-301
93EEThilo Streichert, Christian Haubelt, Jürgen Teich: Online hardware/software partitioning in networked embedded systems. ASP-DAC 2005: 982-985
92EES. Helwig, Christian Haubelt, Jürgen Teich: Modeling and analysis of indirect communication in particle swarm optimization. Congress on Evolutionary Computation 2005: 1246-1253
91EEThilo Streichert, Christian Haubelt, Jürgen Teich: Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks. DATE 2005: 894-895
90EEChristian Haubelt, Jürgen Gamenik, Jürgen Teich: Initial Population Construction for Convergence Improvement of MOEAs. EMO 2005: 191-205
89 Frank Hannig, Jürgen Teich: Output Serialization for FPGA-based and Coarse-grained Processor Arrays. ERSA 2005: 78-84
88 Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich: Defragmenting the Module Layout of a Partially Reconfigurable Device. ERSA 2005: 92-104
87EEChristophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform. FCCM 2005: 319-320
86 Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. FPL 2005: 153-158
85 Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich: The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms. FPT 2005: 37-42
84EEThomas Schlichter, Christian Haubelt, Jürgen Teich: Improving EA-based design space exploration by utilizing symbolic feasibility tests. GECCO 2005: 1945-1952
83 Christian Haubelt, Marek Jersak, Kai Richter, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich, Lothar Thiele: SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme. GI Jahrestagung (2) 2005: 693-697
82EEAli Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. IEEE International Workshop on Rapid System Prototyping 2005: 84-90
81EEMateusz Majer, Christophe Bobda, Ali Ahmadinia, Jürgen Teich: Packet Routing in Dynamically Changing Networks on Chip. IPDPS 2005
80EESanaz Mostaghim, Jürgen Teich: A New Approach on Many Objective Diversity Measurement. Practical Approaches to Multi-Objective Optimization 2005
79 Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys: Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34
78EEHolger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich: Automatic FIR Filter Generation for FPGAs. SAMOS 2005: 51-61
77EEAli Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices CoRR abs/cs/0503066: (2005)
76EEJan van der Veen, Sándor P. Fekete, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich: Defragmenting the Module Layout of a Partially Reconfigurable Device CoRR abs/cs/0505005: (2005)
75EEChristophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices CoRR abs/cs/0510039: (2005)
74EEAli Ahmadinia, Christophe Bobda, Jürgen Teich: Online placement for dynamically reconfigurable devices. IJES 1(3/4): 165-178 (2005)
2004
73EEAli Ahmadinia, Christophe Bobda, Jürgen Teich: A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware. ARCS 2004: 125-139
72 Christophe Bobda, Ali Ahmadinia, Jürgen Teich: Generation of Distributed Arithmetic Designs for Reconfigurable Application. ARCS Workshops 2004: 205-214
71EEFrank Hannig, Jürgen Teich: Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. ASAP 2004: 17-27
70EEDirk Koch, Jürgen Teich: Platform-independent methodology for partial reconfiguration. Conf. Computing Frontiers 2004: 398-403
69EEChristophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich: A Dynamic NoC Approach for Communication in Reconfigurable Devices. FPL 2004: 1032-1036
68EEAli Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen: Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices. FPL 2004: 847-851
67EENeal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler: Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms. GECCO (2) 2004: 383-384
66EEAli Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich: A New Approach for On-line Placement on Reconfigurable Devices. IPDPS 2004
65EEFrank Hannig, Hritam Dutta, Jürgen Teich: Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. IPDPS 2004
64EEAli Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich: Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration. IPDPS 2004
63EEFrank Hannig, Jürgen Teich: Dynamic Piecewise Linear/Regular Algorithms. PARELEC 2004: 79-84
62EEChristian Haubelt, Dirk Koch, Jürgen Teich: Basic OS Support for Distributed Reconfigurable Hardware. SAMOS 2004: 30-38
61EEJürgen Teich, Shuvra S. Bhattacharyya: Analysis of Dataflow Programs with Interval-Limited Data-Rates. SAMOS 2004: 507-518
60EEAlexey Kupriyanov, Frank Hannig, Jürgen Teich: High-Speed Event-Driven RTL Compiled Simulation. SAMOS 2004: 519-529
59EEAli Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich: Task scheduling for heterogeneous reconfigurable computers. SBCCI 2004: 22-27
58EEAli Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen: Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices CoRR cs.DS/0406035: (2004)
57 Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler: Systematic integration of parameterized local search into evolutionary algorithms. IEEE Trans. Evolutionary Computation 8(2): 137-155 (2004)
2003
56EEJens Gerling, Oliver Stübbe, Jürgen Schrage, Gerd Mrozynski, Jürgen Teich: Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects. DATE 2003: 11110-11111
55EEChristian Haubelt, Jürgen Teich, Rainer Feldmann, Burkhard Monien: SAT-Based Techniques in System Synthesis. DATE 2003: 11168-11169
54EEOliver Schütze, Sanaz Mostaghim, Michael Dellnitz, Jürgen Teich: Covering Pareto Sets by Multilevel Evolutionary Subdivision Techniques. EMO 2003: 118-132
53EEChristian Haubelt, Sanaz Mostaghim, Jürgen Teich, Ambrish Tyagi: Solving Hierarchical Optimization Problems Using MOEAs. EMO 2003: 162-176
52EERainer Feldmann, Christian Haubelt, Burkhard Monien, Jürgen Teich: Fault Tolerances Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques. FPL 2003: 478-487
51EECornelia Grabbe, Marcus Bednara, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich: A High Performance VLIW Processor for Finite Field Arithmetic. IPDPS 2003: 189
50EECornelia Grabbe, Marcus Bednara, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi: FPGA designs of parallel high performance GF(2233) multipliers. ISCAS (2) 2003: 268-271
49EEChristian Haubelt, Dirk Koch, Jürgen Teich: ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware. SBCCI 2003: 343-348
48 Ali Ahmadinia, Jürgen Teich: Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead. VLSI-SOC 2003: 118-122
47EESándor P. Fekete, Ekkehard Köhler, Jürgen Teich: Higher-Dimensional Packing with Order Constraints CoRR cs.DS/0308006: (2003)
46EEDirk Fischer, Jürgen Teich, Ralph Weper, Michael Thies: BUILDABONG: A Framework for Architecture/Compiler Co-Exploration for ASIPs. Journal of Circuits, Systems, and Computers 12(3): 353- (2003)
45EEMarcus Bednara, Jürgen Teich: Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms. The Journal of Supercomputing 26(2): 149-165 (2003)
2002
44 Ed F. Deprettere, Jürgen Teich, Stamatis Vassiliadis: Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS Springer 2002
43EEDirk Fischer, Jürgen Teich, Michael Thies, Ralph Weper: Efficient architecture/compiler co-exploration for ASIPs. CASES 2002: 27-34
42EEJürgen Teich, Markus Köster: (Self-)reconfigurable Finite State Machines: Theory and Implementation. DATE 2002: 559-567
41EEChristian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst: System Design for Flexibility. DATE 2002: 854-861
40EEJürgen Teich, Lothar Thiele: Exact Partitioning of Affine Dependence Algorithms. Embedded Processor Design Challenges 2002: 135-153
39EEMarcus Bednara, Frank Hannig, Jürgen Teich: Generation of Distributed Loop Control. Embedded Processor Design Challenges 2002: 154-170
38EEChristian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst: Flexibility/Cost-Tradeoffs of Platform-Based Systems. Embedded Processor Design Challenges 2002: 38-56
37EEMarcus Bednara, M. Daldrup, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich: Reconfigurable Implementation of Elliptic Curve Crypto Algorithms. IPDPS 2002
36EEMarcus Bednara, M. Daldrup, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi: Tradeoff analysis of FPGA based elliptic curve cryptography. ISCAS (5) 2002: 797-800
35EEFrank Hannig, Jürgen Teich: Energy estimation of nested loop programs. SPAA 2002: 149-150
34EEDirk Ziegenbein, Kai Richter, Rolf Ernst, Lothar Thiele, Jürgen Teich: SPI - a system model for heterogeneously specified embedded systems. IEEE Trans. VLSI Syst. 10(4): 379-389 (2002)
2001
33EEDirk Fischer, Jürgen Teich, Ralph Weper, Uwe Kastens, Michael Thies: Design space characterization for architecture/compiler co-exploration. CASES 2001: 108-115
32EENeal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler: Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors. CODES 2001: 243-248
31EESándor P. Fekete, Ekkehard Köhler, Jürgen Teich: Optimal FPGA module placement with temporal precedence constraints. DATE 2001: 658-667
30EEJürgen Teich: Pareto-Front Exploration with Uncertain Objectives. EMO 2001: 314-328
29EEFrank Hannig, Jürgen Teich: Design Space Exploration for Massively Parallel Processor Arrays. PaCT 2001: 51-65
28EESándor P. Fekete, Ekkehard Köhler, Jürgen Teich: Higher-Dimensional Packing with Order Constraints. WADS 2001: 300-312
27EESándor P. Fekete, Ekkehard Köhler, Jürgen Teich: Extending Partial Suborders. Electronic Notes in Discrete Mathematics 8: 34-37 (2001)
26EEKarsten Strehl, Lothar Thiele, Matthias Gries, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich: FunState-an internal design representation for codesign. IEEE Trans. VLSI Syst. 9(4): 524-544 (2001)
25 Jürgen Teich, Sándor P. Fekete, Jörg Schepers: Optimization of Dynamic Hardware Reconfigurations. The Journal of Supercomputing 19(1): 57-75 (2001)
2000
24EEMarcus Bednara, Oliver Beyer, Jürgen Teich, Rolf Wanka: Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter. ASAP 2000: 299-308
23EEJürgen Teich, Philipp W. Kutter, Ralph Weper: Description and Simulation of Microprocessor Instruction Sets Using ASMs. Abstract State Machines 2000: 266-286
22EEJürgen Teich, Ralph Weper, Dirk Fischer, Stefan Trinkert: A joined architecture/compiler design environment for ASIPs. CASES 2000: 26-33
21 F. Cieslok, H. Esau, Jürgen Teich: EXPLORA - Generic Design Space Exploration during Embedded System Synthesis. DIPES 2000: 215-226
20EEEckart Zitzler, Jürgen Teich, S. S. Bhattclcharyya: Evolutionary algorithms for the synthesis of embedded software. IEEE Trans. VLSI Syst. 8(4): 452-455 (2000)
19 Lothar Thiele, Jürgen Teich, Karsten Strehl: Regular state machines. Parallel Algorithms Appl. 15(3-4): 265-300 (2000)
18EEEckart Zitzler, Jürgen Teich, Shuvra S. Bhattacharyya: Multidimensional Exploration of Software Implementations for DSP Algorithms. VLSI Signal Processing 24(1): 83-98 (2000)
1999
17EEJürgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya: 3D exploration of software schedules for DSP algorithms. CODES 1999: 168-172
16EEKarsten Strehl, Lothar Thiele, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich: Scheduling hardware/software systems using symbolic techniques. CODES 1999: 173-177
15EEKai Richter, Dirk Ziegenbein, Rolf Ernst, Lothar Thiele, Jürgen Teich: Representation of Function Variants for Embedded System Optimization and Synthesis. DAC 1999: 517-522
14EELothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich: FunState - an internal design representation for codesign. ICCAD 1999: 558-565
13 Jürgen Teich, Sándor P. Fekete, Jörg Schepers: Compile-time Optimization of Dynamic Hardware Reconfigurations. PDPTA 1999: 1097-1103
1998
12EEMichael Eisenring, Jürgen Teich: Domain-specific interface generation from dataflow specifications. CODES 1998: 43-47
11EEDirk Ziegenbein, Rolf Ernst, Kai Richter, Jürgen Teich, Lothar Thiele: Combining multiple models of computation for scheduling and allocation. CODES 1998: 9-13
10EEMichael Eisenring, Jürgen Teich: Interfacing Hardware and Software. FPL 1998: 520-524
9EEDirk Ziegenbein, Kai Richter, Rolf Ernst, Jürgen Teich, Lothar Thiele: Representation of process mode correlation for scheduling. ICCAD 1998: 54-61
8EEJürgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya: Buffer Memory Optimization in DSP Applications - An Evolutionary Approach. PPSN 1998: 885-896
1997
7EEJürgen Teich, Tobias Blickle, Lothar Thiele: An evolutionary approach to system-level synthesis. CODES 1997: 167-172
6EEJürgen Teich, Lothar Thiele, Sundararajan Sriram, Michael Martin: Performance analysis and optimization of mixed asynchronous synchronous systems. IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 473-484 (1997)
5EEJürgen Teich, Lothar Thiele, Lee Z. Zhang: Partitioning Processor Arrays under Resource Constraints. VLSI Signal Processing 17(1): 5-20 (1997)
1996
4EEJürgen Teich, Lothar Thiele, Li Zhang: Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources. ASAP 1996: 131-144
1995
3EEJürgen Teich, Lothar Thiele, Edward A. Lee: Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model. ISSS 1995: 156-161
2EEChristian Schwarz, Jürgen Teich, Alek Vainshtein, Emo Welzl, Brian L. Evans: Minimal Enclosing Parallelogram with Application. Symposium on Computational Geometry 1995: C34-C35
1991
1EEJürgen Teich, Lothar Thiele: Control generation in the design of processor arrays. VLSI Signal Processing 3(1-2): 77-92 (1991)

Coauthor Index

1Ali Ahmadinia [48] [58] [59] [64] [66] [68] [69] [72] [73] [74] [75] [76] [77] [81] [82] [85] [86] [87] [88] [117] [123] [141]
2Josef Angermeier [121] [147] [149] [152] [154] [170]
3Stefan Assmus [105]
4Peter M. Athanas (Peter Athanas) [111] [112] [120]
5Neal K. Bambha [32] [57] [67]
6Ulrich Batzer [170]
7Jürgen Becker [111] [112] [120] [151] [152]
8Christian Beckhoff [153] [171] [175]
9Marcus Bednara [24] [36] [37] [39] [45] [50] [51] [64] [66]
10Oliver Beyer [24]
11Shuvra S. Bhattacharyya [8] [17] [18] [32] [57] [61] [67] [96] [158]
12S. S. Bhattclcharyya [20]
13Tobias Blickle [7]
14Christophe Bobda [58] [59] [64] [66] [68] [69] [72] [73] [74] [75] [76] [77] [81] [82] [85] [86] [87] [88] [117] [123]
15Unmesh D. Bordoloi [180]
16Lars Braun [152]
17Gordon J. Brebner [111] [112] [120]
18Robert Brendle [168]
19Samarjit Chakraborty [180]
20Daniel Chillet [79]
21Kiyoung Choi [138]
22F. Cieslok [21]
23Christopher Claus [149] [152] [170]
24M. Daldrup [36] [37]
25Michael Dellnitz [54]
26Ed F. Deprettere [44]
27Ji Ding [77] [82]
28Steffen Dittrich [118]
29Rainer Dorsch [113]
30Nikil D. Dutt (Nikil Dutt) [138]
31Hritam Dutta [65] [78] [79] [98] [101] [116] [119] [124] [128] [135] [151] [169] [172] [174] [178] [183] [184] [185] [186]
32Sven Eisenhardt [151]
33Michael Eisenring [10] [12]
34Rolf Ernst [9] [11] [14] [15] [16] [26] [34] [38] [41] [83]
35H. Esau [21]
36Brian L. Evans [2]
37Joachim Falk [106] [113] [134] [146] [158] [173]
38Sándor P. Fekete [13] [25] [27] [28] [31] [47] [58] [68] [75] [76] [77] [82] [86] [87] [88] [97] [104] [121] [141] [154]
39Rainer Feldmann [52] [55]
40Julio A. de Oliveira Filho [151]
41Dirk Fischer [22] [33] [43] [46]
42Krisztián Flautner [107]
43Jürgen Gamenik [90]
44Joachim von zur Gathen [36] [37] [50] [51]
45Jens Gerling [56]
46Michael Glabeta [163]
47Jens Gladigau [133] [155] [173]
48Michael Glaß [109] [125] [127] [130] [136] [142] [144] [148] [161] [162] [165] [166] [176] [177] [180] [181] [182]
49Manfred Glesner [151]
50Diana Göhringer [110] [121] [141]
51Cornelia Grabbe [50] [51] [94]
52Philipp Graf [152]
53Matthias Gries [26]
54Soonhoi Ha [138]
55Thomas Haller [85] [87]
56Frank Hannig [29] [35] [39] [60] [63] [65] [71] [76] [78] [79] [88] [89] [95] [98] [100] [101] [115] [116] [119] [124] [126] [128] [135] [137] [145] [150] [151] [156] [159] [160] [169] [172] [174] [178] [183] [184] [185] [186]
57Christian Haubelt [38] [41] [49] [52] [53] [55] [62] [83] [84] [90] [91] [92] [93] [94] [95] [99] [102] [103] [106] [109] [113] [118] [125] [127] [129] [130] [131] [132] [133] [134] [136] [142] [146] [148] [155] [157] [158] [161] [162] [163] [165] [166] [167] [168] [173] [176] [177] [178]
58Benno Heigl [116]
59S. Helwig [92]
60Andreas Herkersdorf [152]
61Heiko Hinkelmann [151]
62Heinz Hornegger [116]
63Michael Hübner [152]
64Marek Jersak [83]
65Tom Kamphans (Thomas Kamphans) [154]
66Uwe Kastens [33]
67Stefanos Kaxiras [107]
68Joachim Keinert [131] [134] [158] [163] [167] [173] [178]
69Ronan Keryell [79]
70Dmitrij Kissler [100] [115] [126] [128] [135] [137] [145] [151] [172]
71Dirk Koch [49] [59] [62] [69] [70] [108] [115] [118] [129] [132] [153] [154] [157] [168] [171] [175]
72Matthiaas Koerber [108]
73Ekkehard Köhler [27] [28] [31] [47] [97]
74Markus Köster (Markus Koester) [42]
75Matthias Kovatsch [149]
76Krzysztof Kuchcinski [150] [156] [160]
77Alexey Kupriyanov [60] [79] [100] [115] [126] [128] [137] [172]
78Philipp W. Kutter [23]
79Philipp Kutzer [183]
80Julien Lallet [137]
81Bardo Lang [162]
82Edward A. Lee [3]
83André Linarth [85] [87]
84Enno Lübbers [152]
85Martin Lukasiewycz [102] [109] [127] [130] [136] [142] [144] [148] [161] [162] [163] [165] [176] [177] [180] [181] [182]
86Mateusz Majer [59] [69] [75] [77] [81] [82] [85] [86] [87] [88] [104] [110] [117] [121] [123] [141] [152] [170]
87Michael Martin [6]
88Richard Membarth [174] [183]
89Daniel Menard [79]
90Michael Meredith [173]
91Renate Merker [79] [128] [152] [159]
92Paul Milbredt [181]
93Burkhard Monien [52] [55]
94Sanaz Mostaghim [53] [54] [80]
95Gerd Mrozynski [56]
96Bernhard Niemann [133]
97Tobias Oppold [151]
98Stephan Otto [94]
99Sébastien Pillement [137]
100Toomas P. Plaks [107]
101Marco Platzner [152]
102Bernard Pottier [79] [128] [172]
103Richard Regler [162]
104Felix Reimann [142] [161] [163]
105Kai Richter [9] [11] [15] [34] [38] [41] [83]
106Wolfgang Rosenstiel [151]
107Holger Ruckdeschel [78] [124] [135] [169]
108Markus Rullmann [152]
109Rainer Schaffer [79] [128] [159]
110Jörg Schepers [13] [25]
111Thomas Schlichter [84] [95] [102] [173]
112Thomas Schlipf [113]
113Jürgen Schrage [56]
114Oliver Schütze [54]
115T. Schwalb [152]
116Christian Schwarz [2]
117Nils Schweer [154]
118Thomas Schweizer [151]
119Olivier Sentieys [79] [137]
120Jamshid Shokrollahi [36] [37] [50] [51]
121Sebastian Siegel [79] [128]
122Sundararajan Sriram [6]
123Walter Stechele [149] [152] [170]
124Andrej Stravet [135]
125Andreas Strawetz [145]
126Karsten Strehl [14] [16] [19] [26] [83]
127Thilo Streichert [91] [93] [99] [103] [118] [125] [129] [136] [166] [168]
128Christian Strengert [99] [118]
129Martin Streubühr [113] [173] [176]
130Oliver Stübbe [56]
131Christopher Tessars [154]
132Lothar Thiele [1] [3] [4] [5] [6] [7] [9] [11] [14] [15] [16] [19] [26] [34] [40] [83]
133Michael Thies [33] [43] [46]
134Alexander Thomas [151]
135Stefan Trinkert [22]
136Ambrish Tyagi [53]
137Alek Vainshtein (Alexander Vainshtein) [2]
138Stamatis Vassiliadis [44]
139Jan van der Veen [58] [68] [75] [76] [77] [82] [86] [87] [88] [104] [121] [141] [154]
140Rolf Wanka [24] [166]
141Emo Welzl [2]
142Ralph Weper [22] [23] [33] [43] [46]
143Stefan Wildermann [143] [179]
144Christophe Wolinski [150] [156] [160]
145Christian Zebelein [146]
146Jiali Zhai [184]
147Lee Z. Zhang [5]
148Li Zhang [4]
149Dirk Ziegenbein [9] [11] [14] [15] [16] [26] [34] [83]
150Daniel Ziener [105] [140] [164]
151Tobias Ziermann [179]
152Peter Zipf [151]
153Eckart Zitzler [8] [17] [18] [20] [32] [57] [67]

Colors in the list of coauthors

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