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Sheldon X.-D. Tan Vis

Xiang-Dong Tan

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*2009
88EERuijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. ASP-DAC 2009: 161-166
87EEDuo Li, Sheldon X.-D. Tan, Gengsheng Chen, Xuan Zeng: Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method. ASP-DAC 2009: 272-277
86EEHai Wang, Hao Yu, Sheldon X.-D. Tan: Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling. ASP-DAC 2009: 379-384
85EEJin Shi, Yici Cai, Wenting Hou, Liwei Ma, Sheldon X.-D. Tan, Pei-Hsin Ho, Xiaoyi Wang: GPU friendly fast Poisson solver for structured power grid network analysis. DAC 2009: 178-183
84EEXiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles: An efficient decoupling capacitance optimization using piecewise polynomial models. DATE 2009: 1190-1195
83EEThom Jefferson A. Eguia, Ning Mi, Sheldon X.-D. Tan: Statistical decoupling capacitance allocation by efficient numerical quadrature method. ISQED 2009: 309-316
82EENing Mi, Sheldon X.-D. Tan, Boyuan Yan: Multiple block structure-preserving reduced order modeling of interconnect circuits. Integration 42(2): 158-168 (2009)
81EEDuo Li, Sheldon X.-D. Tan, Lifeng Wu: Hierarchical Krylov subspace based reduction of large interconnects. Integration 42(2): 193-202 (2009)
2008
80EEJian Cui, Gengsheng Chen, Ruijing Shen, Sheldon X.-D. Tan, Wenjian Yu, Jiarong Tong: Variational capacitance modeling using orthogonal polynomial method. ACM Great Lakes Symposium on VLSI 2008: 23-28
79EEPu Liu, Sheldon X.-D. Tan, Wei Wu, Murli Tirumala: FEKIS: a fast architecture-level thermal analyzer for online thermal regulation. ACM Great Lakes Symposium on VLSI 2008: 411-416
78EEDuo Li, Sheldon X.-D. Tan: Hierarchical Krylov subspace reduced order modeling of large RLC circuits. ASP-DAC 2008: 170-175
77EEDuo Li, Sheldon X.-D. Tan, Murli Tirumala: Architecture-level thermal behavioral characterization for multi-core microprocessors. ASP-DAC 2008: 456-461
76EEBoyuan Yan, Lingfei Zhou, Sheldon X.-D. Tan, Jie Chen, Bruce McGaughy: DeMOR: decentralized model order reduction of linear networks with massive ports. DAC 2008: 409-414
75EEDuo Li, Sheldon X.-D. Tan, Bruce McGaughy: ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis. DATE 2008: 432-437
74EEDuo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala: Parameterized transient thermal behavioral modeling for chip multiprocessors. ICCAD 2008: 611-617
73EEBoyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Lifeng Wu: Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method. ICCAD 2008: 744-749
72EEZuying Luo, Sheldon X.-D. Tan: Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method. ISQED 2008: 867-872
71EENing Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 1996-2006 (2008)
70EEYici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan: Large scale P/G grid transient simulation using hierarchical relaxed approach. Integration 41(1): 153-160 (2008)
69EEPu Liu, Sheldon X.-D. Tan, Boyuan Yan, Bruce McGaughy: An efficient terminal and model order reduction algorithm. Integration 41(2): 210-218 (2008)
2007
68EEBoyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy: Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form. ASP-DAC 2007: 355-360
67EEYi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang: Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. ASP-DAC 2007: 367-372
66EELe Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan: Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach. ASP-DAC 2007: 751-756
65EEBoyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy: SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits. DAC 2007: 158-161
64EEJeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Statistical model order reduction for interconnect circuits considering spatial correlations. DATE 2007: 1508-1513
63EENing Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong: Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. ICCAD 2007: 48-53
62EEWei Wu, Sheldon X.-D. Tan, Jun Yang, Shih-Lien Lu: Improving the reliability of on-chip data caches under process variations. ICCD 2007: 325-332
61EEJeffrey Fan, Ning Mi, Sheldon X.-D. Tan: Voltage drop reduction for on-chip power delivery considering leakage current variations. ICCD 2007: 78-83
60EEBoyuan Yan, Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy: Passive Modeling of Interconnects by Waveform Shaping. ISQED 2007: 356-361
59EENing Mi, Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fan, Hao Yu: General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits. ISQED 2007: 633-638
58EEWei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan: Efficient power modeling and software thermal sensing for runtime temperature monitoring. ACM Trans. Design Autom. Electr. Syst. 12(3): (2007)
57EEBao Liu, Sheldon X.-D. Tan: Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs. IEEE Trans. VLSI Syst. 15(11): 1284-1287 (2007)
56EEJin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan, Xianlong Hong: Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 680-692 (2007)
55EEPu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu, Lei He: TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1382-1392 (2007)
54EEJeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Partitioning-based decoupling capacitor budgeting via sequence of linear programming. Integration 40(4): 516-524 (2007)
2006
53EEJin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong: Efficient early stage resonance estimation techniques for C4 package. ASP-DAC 2006: 826-831
52EEWei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan: A systematic method for functional unit power estimation in microprocessors. DAC 2006: 554-557
51EENing Mi, Jeffrey Fan, Sheldon X.-D. Tan: Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation. ICCD 2006
50EEAndrew B. Kahng, Bao Liu, Sheldon X.-D. Tan: Efficient decoupling capacitor planning via convex programming methods. ISPD 2006: 102-107
49EEJin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong: High accurate pattern based precondition method for extremely large power/ground grid analysis. ISPD 2006: 108-113
48EEJeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming. ISQED 2006: 272-277
47EEPu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu: Compact Reduced Order Modeling for Multiple-Port Interconnects. ISQED 2006: 413-418
46EEAndrew B. Kahng, Bao Liu, Sheldon X.-D. Tan: SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching. ISQED 2006: 638-643
45EEHang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2402-2412 (2006)
44EEPu Liu, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang: Fast Thermal Simulation for Runtime Temperature Tracking and Management. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2882-2893 (2006)
43EEZhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, Lei He: Wideband passive multiport model order reduction and realization of RLCM circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1496-1509 (2006)
42EEZuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu: Time-domain analysis methodology for large-scale RLC circuits and its applications. Science in China Series F: Information Sciences 49(5): 665-680 (2006)
2005
41EEYici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu: Relaxed hierarchical power/ground grid analysis. ASP-DAC 2005: 1090-1093
40EEHao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan: A wideband hierarchical circuit reduction for massively coupled interconnects. ASP-DAC 2005: 111-114
39EEZhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He: Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction. ASP-DAC 2005: 224-229
38EEJingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan: VLSI on-chip power/ground network optimization considering decap leakage currents. ASP-DAC 2005: 735-738
37EEYi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan: Analysis of buffered hybrid structured clock networks. ASP-DAC 2005: 93-98
36EEHang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Partitioning-based approach to fast on-chip decap budgeting and minimization. DAC 2005: 170-175
35EERoman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan: A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation. FCCM 2005: 57-62
34 Pu Liu, Zhenyu Qi, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang: Fast thermal simulation for architecture level dynamic thermal management. ICCAD 2005: 639-644
33 Pu Liu, Sheldon X.-D. Tan, Hang Li, Zhenyu Qi, Jun Kong, Bruce McGaughy, Lei He: An efficient method for terminal reduction of interconnect circuits considering delay variations. ICCAD 2005: 821-826
32EEHang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang: Efficient Thermal Simulation for Run-Time Temperature Tracking and Management. ICCD 2005: 130-136
31EEZhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. ISQED 2005: 542-547
30EEPu Liu, Zhenyu Qi, Sheldon X.-D. Tan: Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits. ISQED 2005: 603-608
29EEJin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan: Efficient Simulation of Power/Ground Networks with Package and Vias. PATMOS 2005: 318-328
28EESheldon X.-D. Tan: A general hierarchical circuit modeling and simulation algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 418-434 (2005)
27EESheldon X.-D. Tan, Weikun Guo, Zhenyu Qi: Hierarchical approach to exact symbolic analysis of large analog circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1241-1250 (2005)
26EEYi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan: A Fast Delay Computation for the Hybrid Structured Clock Network. IEICE Transactions 88-A(7): 1964-1970 (2005)
2004
25EEJingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan: A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery. ASP-DAC 2004: 505-510
24EESheldon X.-D. Tan, Weikun Guo, Zhenyu Qi: Hierarchical approach to exact symbolic analysis of large analog circuits. DAC 2004: 860-863
23EERoman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan: Dynamic FPGA routing for just-in-time FPGA compilation. DAC 2004: 954-959
22EESheldon X.-D. Tan, Zhenyu Qi, Hang Li: Hierarchical Modeling and Simulation of Large Analog Circuits. DATE 2004: 740-741
21EEYi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan: A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. ICCD 2004: 344-349
20 Junjie Yang, Sheldon X.-D. Tan: Behavioural modelling of analog circuits by dynamic semi-symbolic analysis. ISCAS (5) 2004: 105-108
19 Junjie Yang, Sheldon X.-D. Tan: An efficient algorithm for transient and distortion analysis of mildly nonlinear analog circuits. ISCAS (5) 2004: 129-132
18 Weikun Guo, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong: Partial random walk for large linear network analysis. ISCAS (5) 2004: 173-177
17EEZhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong: Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling. ISQED 2004: 63-68
16EEJingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan: Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery. PATMOS 2004: 433-441
15EESheldon X.-D. Tan, C.-J. Richard Shi: Efficient approximation of symbolic expressions for analog behavioral modeling and analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 907-918 (2004)
2003
14EESheldon X.-D. Tan: A General S-Domain Hierarchical Network Reduction Algorithm. ICCAD 2003: 650-657
13EEQi-De Qian, Sheldon X.-D. Tan: Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis. ISQED 2003: 125-130
12EESheldon X.-D. Tan, C.-J. Richard Shi, Jyh-Chwen Lee: Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings. IEEE Trans. on CAD of Integrated Circuits and Systems 22(12): 1678-1684 (2003)
11EESheldon X.-D. Tan, C.-J. Richard Shi: Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 277-284 (2003)
10EESheldon X.-D. Tan, C.-J. Richard Shi: Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis. Integration 34(1-2): 65-86 (2003)
2001
9EESheldon X.-D. Tan, C.-J. Richard Shi: Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling. DAC 2001: 550-554
8EEC.-J. Richard Shi, Sheldon X.-D. Tan: Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design. IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 813-827 (2001)
2000
7EEXiang-Dong Tan, C.-J. Richard Shi: Symbolic circuit-noise analysis and modeling with determinant decision diagrams. ASP-DAC 2000: 283-288
6EEC.-J. Richard Shi, Sheldon X.-D. Tan: Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 1-18 (2000)
5EESheldon X.-D. Tan, C.-J. Richard Shi: Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 401-412 (2000)
1999
4EEXiang-Dong Tan, C.-J. Richard Shi: Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis. ASP-DAC 1999: 1-4
3EEXiang-Dong Tan, C.-J. Richard Shi, Dragos Lungeanu, Jyh-Chwen Lee, Li-Pen Yuan: Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings. DAC 1999: 78-83
2EEXiang-Dong Tan, C.-J. Richard Shi: Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams. DATE 1999: 448-453
1997
1EEC.-J. Richard Shi, Xiang-Dong Tan: Symbolic analysis of large analog circuits with determinant decision diagrams. ICCAD 1997: 366-373

Coauthor Index

1Yici Cai [16] [17] [21] [25] [26] [29] [31] [36] [37] [38] [41] [42] [45] [48] [49] [53] [54] [56] [63] [64] [66] [67] [70] [71] [84] [85] [88]
2Gengsheng Chen [73] [80] [87]
3Jie Chen [76]
4Jian Cui [63] [80]
5Thom Jefferson A. Eguia [83]
6Jeffrey Fan [45] [48] [51] [54] [56] [59] [61] [64]
7Jingjing Fu [16] [25] [38] [42]
8Weikun Guo [18] [24] [27]
9Lei He [33] [39] [40] [43] [55]
10Pei-Hsin Ho [85]
11Xianlong Hong [16] [17] [18] [21] [25] [26] [29] [31] [36] [37] [38] [41] [42] [45] [48] [49] [53] [54] [56] [63] [64] [66] [67] [70] [71] [84] [88]
12Wenting Hou [41] [85]
13Lingling Jin [32] [34] [44] [52] [58]
14Andrew B. Kahng [46] [50]
15Le Kang [66] [67]
16Jun Kong [33]
17Jyh-Chwen Lee [3] [12]
18Duo Li [74] [75] [77] [78] [81] [87]
19Hang Li [22] [31] [32] [33] [34] [36] [44] [45]
20I-Fan Liao [48]
21Bao Liu [46] [50] [57]
22Pu Liu [30] [32] [33] [34] [43] [44] [47] [52] [55] [58] [60] [63] [65] [68] [69] [79]
23Shih-Lien Lu [62]
24Dragos Lungeanu [3]
25Zuying Luo [16] [17] [18] [25] [38] [42] [72]
26Roman L. Lysecky [23] [35]
27Liwei Ma [85]
28Bruce McGaughy [33] [47] [55] [60] [65] [68] [69] [75] [76]
29Ning Mi [51] [59] [61] [63] [64] [71] [82] [83] [88]
30Eduardo H. Pacheco [74]
31Zhu Pan [16] [17] [25] [38] [41] [42] [70]
32Zhenyu Qi [22] [24] [27] [30] [31] [32] [33] [34] [36] [39] [40] [43] [45]
33Qi-De Qian [13]
34Jacob Relles [84]
35Ruijing Shen [80] [88]
36C.-J. Richard Shi [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [15]
37Jin Shi [29] [49] [53] [56] [66] [70] [85]
38Murli Tirumala [74] [77] [79]
39Jiarong Tong [80]
40Frank Vahid [23] [35]
41Hai Wang [86]
42Xiaoyi Wang [42] [84] [85]
43Lifeng Wu [31] [36] [41] [45] [47] [55] [73] [81]
44Wei Wu [32] [34] [44] [52] [58] [62] [79]
45Boyuan Yan [59] [60] [65] [68] [69] [73] [76] [82]
46Jun Yang [32] [34] [44] [52] [58] [62]
47Junjie Yang [19] [20]
48Hao Yu [39] [40] [43] [59] [86]
49Wenjian Yu [80]
50Li-Pen Yuan [3]
51Xuan Zeng [87]
52Lingfei Zhou [76]
53Qiang Zhou [21] [26] [37] [67]
54Yi Zou [21] [26] [37] [66] [67]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)