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Kesava R. Talupuru Vis

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*2008
2EEKyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang: Simulation Acceleration with HW Re-Compilation Avoidance. VLSI Design 2008: 487-491
2005
1EEZhihong Zeng, Kesava R. Talupuru, Maciej J. Ciesielski: Functional test generation based on word-level SAT. Journal of Systems Architecture 51(8): 488-511 (2005)

Coauthor Index

1Maciej J. Ciesielski [1] [2]
2Kyuho Shim [2]
3Seiyang Yang [2]
4Zhihong Zeng [1]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)