Coauthor Index - Ask others: ACM DL/Guide - CiteSeerX - CSB - MetaPress - Google - Bing - Yahoo

* | 2009 | |
---|---|---|

154 | EE | Vineeth Veetil, Dennis Sylvester, David Blaauw, Saumil Shah, Steffen Rochel: Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence. DAC 2009: 154-159 |

153 | EE | David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David Blaauw, Dennis Sylvester: Vicis: a reliable network for unreliable silicon. DAC 2009: 812-817 |

152 | EE | David Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David Blaauw: A highly resilient routing algorithm for fault-tolerant NoCs. DATE 2009: 21-26 |

151 | EE | Ronald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Reconfigurable Multicore Server Processors for Low Power Operation. SAMOS 2009: 247-254 |

2008 | ||

150 | EE | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester: Investigation of diffusion rounding for post-lithography analysis. ASP-DAC 2008: 480-485 |

149 | EE | Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown: Clock tree synthesis with data-path sensitivity matching. ASP-DAC 2008: 498-503 |

148 | EE | Vineeth Veetil, Dennis Sylvester, David Blaauw: Efficient Monte Carlo based incremental statistical timing analysis. DAC 2008: 676-681 |

147 | EE | Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Leakage power reduction using stress-enhanced layouts. DAC 2008: 912-917 |

146 | EE | Ravikishore Gandikota, David Blaauw, Dennis Sylvester: Modeling crosstalk in statistical static timing analysis. DAC 2008: 974-979 |

145 | EE | Jae-sun Seo, Igor L. Markov, Dennis Sylvester, David Blaauw: On the decreasing significance of large standard cells in technology mapping. ICCAD 2008: 116-121 |

144 | EE | Brian Cline, Vivek Joshi, Dennis Sylvester, David Blaauw: STEEL: a technique for stress-enhanced standard cell library design. ICCAD 2008: 691-697 |

143 | EE | Kaviraj Chopra, Cheng Zhuo, David Blaauw, Dennis Sylvester: A statistical approach for full-chip gate-oxide reliability analysis. ICCAD 2008: 698-705 |

142 | EE | Yu-Shiang Lin, Scott Hanson, Fabio Albano, Carlos Tokunaga, Razi-Ul Haque, Kensall Wise, Ann Marie Sastry, David Blaauw, Dennis Sylvester: Low-voltage circuit design for widespread sensing applications. ISCAS 2008: 2558-2561 |

141 | EE | Himanshu Kaul, Jae-sun Seo, Mark Anders, Dennis Sylvester, Ram Krishnamurthy: A robust alternate repeater technique for high performance busses in the multi-core era. ISCAS 2008: 372-375 |

140 | EE | Cheng Zhuo, David Blaauw, Dennis Sylvester: Variation-aware gate sizing and clustering for post-silicon optimized circuits. ISLPED 2008: 105-110 |

139 | EE | Mingoo Seok, Dennis Sylvester, David Blaauw: Optimal technology selection for minimizing energy and variability in low voltage applications. ISLPED 2008: 9-14 |

138 | EE | Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Stress aware layout optimization. ISPD 2008: 168-174 |

137 | EE | Eric Karl, Dennis Sylvester, David Blaauw: Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures. ISQED 2008: 391-395 |

136 | EE | Vineeth Veetil, Dennis Sylvester, David Blaauw: Fast and Accurate Waveform Analysis with Current Source Models. ISQED 2008: 53-56 |

135 | EE | Ronald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David Blaauw, Dennis Sylvester, Krisztián Flautner: Reconfigurable energy efficient near threshold cache architectures. MICRO 2008: 459-470 |

134 | EE | Eric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Multi-Mechanism Reliability Modeling and Management in Dynamic Systems. IEEE Trans. VLSI Syst. 16(4): 476-487 (2008) |

133 | EE | Prashant Singh, Jae-sun Seo, David Blaauw, Dennis Sylvester: Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect. IEEE Trans. VLSI Syst. 16(6): 673-677 (2008) |

132 | EE | Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw: A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 272-285 (2008) |

131 | EE | Dennis Sylvester, Kanak Agarwal, Saumil Shah: Variability in nanometer CMOS: Impact, analysis, and minimization. Integration 41(3): 319-339 (2008) |

2007 | ||

130 | EE | Youngmin Kim, Dusan Petranovic, Dennis Sylvester: Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion. ASP-DAC 2007: 456-461 |

129 | EE | Yu-Shiang Lin, Dennis Sylvester: Runtime leakage power estimation technique for combinational circuits. ASP-DAC 2007: 660-665 |

128 | EE | Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer: Top-k Aggressors Sets in Delay Noise Analysis. DAC 2007: 174-179 |

127 | EE | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester: Line-End Shortening is Not Always a Failure. DAC 2007: 270-271 |

126 | EE | Mingoo Seok, Scott Hanson, Dennis Sylvester, David Blaauw: Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design. DAC 2007: 694-699 |

125 | EE | Scott Hanson, Mingoo Seok, Dennis Sylvester, David Blaauw: Nanometer Device Scaling in Subthreshold Circuits. DAC 2007: 700-705 |

124 | EE | Gregory K. Chen, David Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim: Yield-driven near-threshold SRAM design. ICCAD 2007: 660-666 |

123 | EE | Vivek Joshi, David Blaauw, Dennis Sylvester: Soft-edge flip-flops for improved timing yield: design and optimization. ICCAD 2007: 667-673 |

122 | EE | Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada: Victim alignment in crosstalk aware timing analysis. ICCAD 2007: 698-704 |

121 | EE | Bo Zhai, Ronald G. Dreslinski, David Blaauw, Trevor N. Mudge, Dennis Sylvester: Energy efficient near-threshold chip multi-processing. ISLPED 2007: 32-37 |

120 | EE | Jae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, Ram Krishnamurthy: A robust edge encoding technique for energy-efficient multi-cycle interconnect. ISLPED 2007: 68-73 |

119 | EE | Jae-sun Seo, Prashant Singh, Dennis Sylvester, David Blaauw: Self-Time Regenerators for High-Speed and Low-Power Interconnect. ISQED 2007: 621-626 |

118 | EE | Ronald G. Dreslinski, Bo Zhai, Trevor N. Mudge, David Blaauw, Dennis Sylvester: An Energy Efficient Parallel Architecture Using Near Threshold Operation. PACT 2007: 175-188 |

117 | EE | Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction CoRR abs/0710.4679: (2007) |

116 | EE | Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge: Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage CoRR abs/0710.4794: (2007) |

115 | EE | H. Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka: Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. IEEE Trans. VLSI Syst. 15(11): 1215-1224 (2007) |

114 | EE | Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown: Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. IEEE Trans. VLSI Syst. 15(6): 613-623 (2007) |

113 | EE | Ashish Srivastava, T. Kachru, Dennis Sylvester: Low-Power-Design Space Exploration Considering Process Variation Using Robust Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 67-79 (2007) |

112 | EE | Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester: Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 468-479 (2007) |

111 | EE | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester: Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1614-1624 (2007) |

2006 | ||

110 | EE | Sarvesh H. Kulkarni, Dennis Sylvester: Power distribution techniques for dual VDD circuits. ASP-DAC 2006: 838-843 |

109 | EE | Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown: Process-induced skew reduction in nominal zero-skew clock trees. ASP-DAC 2006: 84-89 |

108 | EE | Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown: Clock buffer and wire sizing using sequential programming. DAC 2006: 1041-1046 |

107 | EE | Eric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Reliability modeling and management in dynamic microprocessor-based systems. DAC 2006: 1057-1060 |

106 | EE | Sani R. Nassif, Vijay Pitchumani, N. Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic: Variation-aware analysis: savior of the nanometer era? DAC 2006: 411-412 |

105 | EE | Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester: An efficient static algorithm for computing the soft error rates of combinational circuits. DATE 2006: 164-169 |

104 | EE | Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester: A new statistical max operation for propagating skewness in statistical timing analysis. ICCAD 2006: 237-243 |

103 | EE | Sarvesh H. Kulkarni, Dennis Sylvester, David Blaauw: A statistical framework for post-silicon tuning through body bias clustering. ICCAD 2006: 39-46 |

102 | EE | Rajeev R. Rao, David Blaauw, Dennis Sylvester: Soft error reduction in combinational logic using gate resizing and flipflop selection. ICCAD 2006: 502-509 |

101 | EE | Harmander Deogun, Dennis Sylvester, Kevin J. Nowka: Fine grained multi-threshold CMOS for enhanced leakage reduction. ISCAS 2006 |

100 | EE | Scott Hanson, Dennis Sylvester, David Blaauw: A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits. ISLPED 2006: 338-341 |

99 | EE | Scott Hanson, Bo Zhai, David Blaauw, Dennis Sylvester, Andres Bryant, Xinlin Wang: Energy optimality and variability in subthreshold design. ISLPED 2006: 363-365 |

98 | EE | Harmander Deogun,
Robert M. Senger,
Dennis Sylvester,
Richard B. Brown,
Kevin J. Nowka:
A dual-V_{DD} boosted pulsed bus technique for low power and low leakage operation.
ISLPED 2006: 73-78 |

97 | EE | Vivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester: Logic SER Reduction through Flipflop Redesign. ISQED 2006: 611-616 |

96 | EE | Kanak Agarwal, Kevin J. Nowka, Harmander Deogun, Dennis Sylvester: Power Gating with Multiple Sleep Modes. ISQED 2006: 633-637 |

95 | EE | Scott Hanson, Bo Zhai, Kerry Bernstein, David Blaauw, Andres Bryant, Leland Chang, Koushik K. Das, Wilfried Haensch, Edward J. Nowak, Dennis Sylvester: Ultralow-voltage, minimum-energy CMOS. IBM Journal of Research and Development 50(4-5): 469-490 (2006) |

94 | EE | Dennis Sylvester, David Blaauw, Eric Karl: ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon. IEEE Design & Test of Computers 23(6): 484-490 (2006) |

93 | EE | Dongwoo Lee, David Blaauw, Dennis Sylvester: Runtime Leakage Minimization Through Probability-Aware Optimization. IEEE Trans. VLSI Syst. 14(10): 1075-1088 (2006) |

92 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw: Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 892-901 (2006) |

91 | EE | Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David Blaauw: Statistical interconnect metrics for physical-design optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1273-1288 (2006) |

90 | EE | Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester: Gate-length biasing for runtime-leakage control. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1475-1485 (2006) |

89 | EE | Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Analytical yield prediction considering leakage/performance correlation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1685-1695 (2006) |

88 | EE | Sarvesh H. Kulkarni, Dennis Sylvester: Power Distribution Techniques for Dual VDD Circuits. J. Low Power Electronics 2(2): 217-229 (2006) |

2005 | ||

87 | EE | Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown: Optimization objectives and models of variation for statistical gate sizing. ACM Great Lakes Symposium on VLSI 2005: 313-316 |

86 | EE | Robert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge: Total leakage optimization strategies for multi-level caches. ACM Great Lakes Symposium on VLSI 2005: 381-384 |

85 | EE | Himanshu Kaul, Dennis Sylvester: A novel buffer circuit for energy efficient signaling in dual-VDD systems. ACM Great Lakes Symposium on VLSI 2005: 462-467 |

84 | EE | Kanak Agarwal,
Dennis Sylvester,
David Blaauw,
Anirudh Devgan:
Achieving continuous V_{T} performance in a dual V_{T} process.
ASP-DAC 2005: 393-398 |

83 | EE | Dongwoo Lee, David Blaauw, Dennis Sylvester: Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment. ASP-DAC 2005: 399-404 |

82 | EE | Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David Blaauw: Statistical modeling of cross-coupling effects in VLSI interconnects. ASP-DAC 2005: 503-506 |

81 | EE | Jie Yang, Luigi Capodieci, Dennis Sylvester: Advanced timing analysis based on post-OPC extraction of critical dimensions. DAC 2005: 359-364 |

80 | EE | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester: Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. DAC 2005: 365-368 |

79 | EE | Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director: Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. DAC 2005: 535-540 |

78 | EE | Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge: Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage. DATE 2005: 650-651 |

77 | EE | Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction. DATE 2005: 80-85 |

76 | Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester: Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. ICCAD 2005: 1023-1028 | |

75 | Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov: Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. ICCAD 2005: 705-712 | |

74 | EE | Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif: Power-aware global signaling strategies. ISCAS (1) 2005: 604-607 |

73 | EE | Eric Karl, Dennis Sylvester, David Blaauw: Timing error correction techniques for voltage-scalable on-chip memories. ISCAS (4) 2005: 3563-3566 |

72 | EE | Bo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester: Analysis and mitigation of variability in subthreshold design. ISLPED 2005: 20-25 |

71 | EE | Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif: An efficient surface-based low-power buffer insertion algorithm. ISPD 2005: 86-93 |

70 | EE | Harmander Deogun, Dennis Sylvester, David Blaauw: Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate. ISQED 2005: 175-180 |

69 | EE | Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: Performance Driven OPC for Mask Cost Reduction. ISQED 2005: 270-275 |

68 | EE | Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown: Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. ISQED 2005: 284-290 |

67 | EE | Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka: Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. ISQED 2005: 88-93 |

66 | EE | Yu-Shiang Lin, Dennis Sylvester: A New Asymmetric Skewed Buffer Design for Runtime Leakage Power Reduction. VLSI Design 2005: 824-827 |

65 | EE | Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan: Modeling and Analysis of Parametric Yield under Power and Performance Constraints. IEEE Design & Test of Computers 22(4): 376-385 (2005) |

64 | EE | Yu Cao, Xuejue Huang, Dennis Sylvester, Tsu-Jae King, Chenming Hu: Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design. IEEE Trans. VLSI Syst. 13(1): 158-162 (2005) |

63 | EE | Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy: Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses. IEEE Trans. VLSI Syst. 13(11): 1225-1238 (2005) |

62 | EE | Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner: The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. IEEE Trans. VLSI Syst. 13(11): 1239-1252 (2005) |

61 | EE | Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar: Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits. IEEE Trans. VLSI Syst. 13(12): 1362-1375 (2005) |

60 | EE | Rajeev R. Rao, Harmander Deogun, David Blaauw, Dennis Sylvester: Bus encoding for total power reduction using a leakage-aware buffer configuration. IEEE Trans. VLSI Syst. 13(12): 1376-1383 (2005) |

59 | EE | Yu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester: Switch-factor based loop RLC modeling for efficient timing analysis. IEEE Trans. VLSI Syst. 13(9): 1072-1078 (2005) |

58 | EE | Dongwoo Lee, David Blaauw, Dennis Sylvester: Static leakage reduction through simultaneous V/sub t//T/sub ox/ and state assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1014-1029 (2005) |

2004 | ||

57 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw: A simplified transmission-line based crosstalk noise model for on-chip RLC wiring. ASP-DAC 2004: 858-864 |

56 | EE | Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: Toward a methodology for manufacturability-driven design rule exploration. DAC 2004: 311-316 |

55 | EE | Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester: Selective gate-length biasing for cost-effective runtime leakage control. DAC 2004: 327-330 |

54 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula: Variational delay metrics for interconnect timing analysis. DAC 2004: 381-384 |

53 | EE | Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Parametric yield estimation considering leakage variability. DAC 2004: 442-447 |

52 | EE | Anup Kumar Sultania,
Dennis Sylvester,
Sachin S. Sapatnekar:
Tradeoffs between date oxide leakage and delay for dual T_{ox} circuits.
DAC 2004: 761-766 |

51 | EE | Ashish Srivastava, Dennis Sylvester, David Blaauw: Statistical optimization of leakage power considering process variations using dual-Vth and sizing. DAC 2004: 773-778 |

50 | EE | Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw: Leakage-and crosstalk-aware bus encoding for total power reduction. DAC 2004: 779-782 |

49 | EE | Ashish Srivastava, Dennis Sylvester, David Blaauw: Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. DAC 2004: 783-787 |

48 | EE | Bo Zhai, David Blaauw, Dennis Sylvester, Krisztián Flautner: Theoretical and practical limits of dynamic voltage scaling. DAC 2004: 868-873 |

47 | EE | Dongwoo Lee, Harmander Deogun, David Blaauw, Dennis Sylvester: Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization. DATE 2004: 494-499 |

46 | EE | Ashish Srivastava, Dennis Sylvester, David Blaauw: Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design. DATE 2004: 718-719 |

45 | EE | Ashish Srivastava, Dennis Sylvester: A general framework for probabilistic low-power design space exploration considering process variation. ICCAD 2004: 808-813 |

44 | EE | Saumil Shah, Kanak Agarwal, Dennis Sylvester: A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters. ICCD 2004: 138-143 |

43 | EE | Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar: Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits. ICCD 2004: 228-233 |

42 | EE | Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif: Approaches to run-time and standby mode leakage reduction in global buses. ISLPED 2004: 188-193 |

41 | EE | Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy: Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. ISLPED 2004: 194-199 |

40 | EE | Sarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester: A new algorithm for improved VDD assignment in low power dual VDD systems. ISLPED 2004: 200-205 |

39 | EE | Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester: The great interconnect buffering debate: are you a chicken or an ostrich? ISPD 2004: 61 |

38 | EE | Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester: Investigation of performance metrics for interconnect stack architectures. SLIP 2004: 23-29 |

37 | Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 131-139 (2004) | |

36 | Dongwoo Lee, David Blaauw, Dennis Sylvester: Gate oxide leakage current analysis and reduction for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 155-166 (2004) | |

35 | Himanshu Kaul, Dennis Sylvester: Low-power on-chip communication based on transition-aware global signaling (TAGS). IEEE Trans. VLSI Syst. 12(5): 464-476 (2004) | |

34 | EE | Sarvesh H. Kulkarni,
Dennis Sylvester:
High performance level conversion for dual V_{DD} design.
IEEE Trans. VLSI Syst. 12(9): 926-936 (2004) |

33 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driver output model for on-chip RLC transmission lines. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 128-136 (2004) |

32 | EE | Ashish Srivastava, Dennis Sylvester: Minimizing total power by simultaneous V/sub dd//V/sub th/ assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 665-677 (2004) |

31 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw: A simple metric for slew rate of RC circuits based on two circuit moments. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1346-1354 (2004) |

2003 | ||

30 | Dennis Sylvester, Dirk Stroobandt, Louis Scheffer, Payman Zarkesh-Ha: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings ACM 2003 | |

29 | EE | Jan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang: Reshaping EDA for power. DAC 2003: 15 |

28 | EE | Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. DAC 2003: 16-21 |

27 | EE | Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Analysis and minimization techniques for total leakage considering gate oxide leakage. DAC 2003: 175-180 |

26 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw: An effective capacitance based driver output model for on-chip RLC interconnects. DAC 2003: 376-381 |

25 | EE | Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni: Pushing ASIC performance in a power envelope. DAC 2003: 788-793 |

24 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw: Simple metrics for slew rate of RC circuits based on two circuit moments. DAC 2003: 950-953 |

23 | EE | Yu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester: Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis. ICCAD 2003: 848-854 |

22 | EE | Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester: Optimal Inductance for On-chip RLC Interconnections. ICCD 2003: 264- |

21 | EE | Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical estimation of leakage current considering inter- and intra-die process variation. ISLPED 2003: 84-89 |

20 | EE | Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design. ISQED 2003: 287-292 |

19 | EE | Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw: An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. ISVLSI 2003: 149-154 |

18 | EE | Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester: Improved a priori interconnect predictions and technology extrapolation in the GTX system. IEEE Trans. VLSI Syst. 11(1): 3-14 (2003) |

17 | EE | Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu: Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 560-572 (2003) |

2002 | ||

16 | EE | Himanshu Kaul, Dennis Sylvester, David Blaauw: Active shields: a new approach to shielding global wires. ACM Great Lakes Symposium on VLSI 2002: 112-117 |

15 | EE | Ashish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester: Modeling and analysis of leakage power considering within-die process variations. ISLPED 2002: 64-67 |

14 | EE | Himanshu Kaul, Dennis Sylvester: Transition Aware Global Signaling (TAGS). ISQED 2002: 53- |

13 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driving point model for on-chip RLC interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 63-69 |

12 | EE | Himanshu Kaul, Dennis Sylvester, David Blaauw: Active shielding of RLC global interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 98-104 |

11 | EE | Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu: Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. VLSI Design 2002: 77- |

10 | EE | Yu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu: Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. IEEE Trans. VLSI Syst. 10(6): 799-805 (2002) |

2001 | ||

9 | EE | Dennis Sylvester, Himanshu Kaul: Future Performance Challenges in Nanometer Design. DAC 2001: 3-8 |

8 | EE | Dennis Sylvester, Himanshu Kaul: Power-Driven Challenges in Nanometer Design. IEEE Design & Test of Computers 18(6): 12-22 (2001) |

2000 | ||

7 | EE | Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester: GTX: the MARCO GSRC technology extrapolation system. DAC 2000: 693-698 |

6 | Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester: Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. ICCAD 2000: 56-61 | |

5 | EE | Dennis Sylvester: Measurement techniques and interconnect estimation. SLIP 2000: 79-81 |

4 | EE | Dennis Sylvester, Kurt Keutzer: A global wiring paradigm for deep submicron design. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 242-252 (2000) |

1999 | ||

3 | EE | Dennis Sylvester, Kurt Keutzer: Getting to the bottom of deep submicron II: a global wiring paradigm. ISPD 1999: 193-200 |

2 | Dennis Sylvester, Kurt Keutzer: Rethinking Deep-Submicron Circuit Design. IEEE Computer 32(11): 25-33 (1999) | |

1998 | ||

1 | EE | Dennis Sylvester, Kurt Keutzer: Getting to the bottom of deep submicron. ICCAD 1998: 203-211 |