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Dennis Sylvester

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2008
133EEPuneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester: Investigation of diffusion rounding for post-lithography analysis. ASP-DAC 2008: 480-485
132EEMatthew R. Guthaus, Dennis Sylvester, Richard B. Brown: Clock tree synthesis with data-path sensitivity matching. ASP-DAC 2008: 498-503
131EEVivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Stress aware layout optimization. ISPD 2008: 168-174
130EEAshish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw: A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 272-285 (2008)
2007
129EEYoungmin Kim, Dusan Petranovic, Dennis Sylvester: Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion. ASP-DAC 2007: 456-461
128EEYu-Shiang Lin, Dennis Sylvester: Runtime leakage power estimation technique for combinational circuits. ASP-DAC 2007: 660-665
127EERavikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer: Top-k Aggressors Sets in Delay Noise Analysis. DAC 2007: 174-179
126EEPuneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester: Line-End Shortening is Not Always a Failure. DAC 2007: 270-271
125EEMingoo Seok, Scott Hanson, Dennis Sylvester, David Blaauw: Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design. DAC 2007: 694-699
124EEScott Hanson, Mingoo Seok, Dennis Sylvester, David Blaauw: Nanometer Device Scaling in Subthreshold Circuits. DAC 2007: 700-705
123EEGregory K. Chen, David Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim: Yield-driven near-threshold SRAM design. ICCAD 2007: 660-666
122EEVivek Joshi, David Blaauw, Dennis Sylvester: Soft-edge flip-flops for improved timing yield: design and optimization. ICCAD 2007: 667-673
121EERavikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada: Victim alignment in crosstalk aware timing analysis. ICCAD 2007: 698-704
120EEBo Zhai, Ronald G. Dreslinski, David Blaauw, Trevor N. Mudge, Dennis Sylvester: Energy efficient near-threshold chip multi-processing. ISLPED 2007: 32-37
119EEJae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, Ram Krishnamurthy: A robust edge encoding technique for energy-efficient multi-cycle interconnect. ISLPED 2007: 68-73
118EEJae-sun Seo, Prashant Singh, Dennis Sylvester, David Blaauw: Self-Time Regenerators for High-Speed and Low-Power Interconnect. ISQED 2007: 621-626
117EEHimanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction CoRR abs/0710.4679: (2007)
116EERobert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge: Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage CoRR abs/0710.4794: (2007)
115EEH. Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka: Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. IEEE Trans. VLSI Syst. 15(11): 1215-1224 (2007)
114EEKanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown: Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. IEEE Trans. VLSI Syst. 15(6): 613-623 (2007)
113EEAshish Srivastava, T. Kachru, Dennis Sylvester: Low-Power-Design Space Exploration Considering Process Variation Using Robust Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 67-79 (2007)
112EERajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester: Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 468-479 (2007)
111EEPuneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester: Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1614-1624 (2007)
2006
110EESarvesh H. Kulkarni, Dennis Sylvester: Power distribution techniques for dual VDD circuits. ASP-DAC 2006: 838-843
109EEMatthew R. Guthaus, Dennis Sylvester, Richard B. Brown: Process-induced skew reduction in nominal zero-skew clock trees. ASP-DAC 2006: 84-89
108EEMatthew R. Guthaus, Dennis Sylvester, Richard B. Brown: Clock buffer and wire sizing using sequential programming. DAC 2006: 1041-1046
107EEEric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Reliability modeling and management in dynamic microprocessor-based systems. DAC 2006: 1057-1060
106EESani R. Nassif, Vijay Pitchumani, N. Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic: Variation-aware analysis: savior of the nanometer era? DAC 2006: 411-412
105EERajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester: An efficient static algorithm for computing the soft error rates of combinational circuits. DATE 2006: 164-169
104EEKaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester: A new statistical max operation for propagating skewness in statistical timing analysis. ICCAD 2006: 237-243
103EESarvesh H. Kulkarni, Dennis Sylvester, David Blaauw: A statistical framework for post-silicon tuning through body bias clustering. ICCAD 2006: 39-46
102EERajeev R. Rao, David Blaauw, Dennis Sylvester: Soft error reduction in combinational logic using gate resizing and flipflop selection. ICCAD 2006: 502-509
101EEHarmander Deogun, Dennis Sylvester, Kevin J. Nowka: Fine grained multi-threshold CMOS for enhanced leakage reduction. ISCAS 2006
100EEScott Hanson, Dennis Sylvester, David Blaauw: A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits. ISLPED 2006: 338-341
99EEScott Hanson, Bo Zhai, David Blaauw, Dennis Sylvester, Andres Bryant, Xinlin Wang: Energy optimality and variability in subthreshold design. ISLPED 2006: 363-365
98EEHarmander Deogun, Robert M. Senger, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka: A dual-VDD boosted pulsed bus technique for low power and low leakage operation. ISLPED 2006: 73-78
97EEVivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester: Logic SER Reduction through Flipflop Redesign. ISQED 2006: 611-616
96EEKanak Agarwal, Kevin J. Nowka, Harmander Deogun, Dennis Sylvester: Power Gating with Multiple Sleep Modes. ISQED 2006: 633-637
95EEScott Hanson, Bo Zhai, Kerry Bernstein, David Blaauw, Andres Bryant, Leland Chang, Koushik K. Das, Wilfried Haensch, Edward J. Nowak, Dennis Sylvester: Ultralow-voltage, minimum-energy CMOS. IBM Journal of Research and Development 50(4-5): 469-490 (2006)
94EEDongwoo Lee, David Blaauw, Dennis Sylvester: Runtime Leakage Minimization Through Probability-Aware Optimization. IEEE Trans. VLSI Syst. 14(10): 1075-1088 (2006)
93EEKanak Agarwal, Dennis Sylvester, David Blaauw: Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 892-901 (2006)
92EEKanak Agarwal, Mridul Agarwal, Dennis Sylvester, David Blaauw: Statistical interconnect metrics for physical-design optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1273-1288 (2006)
91EEPuneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester: Gate-length biasing for runtime-leakage control. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1475-1485 (2006)
90EERajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Analytical yield prediction considering leakage/performance correlation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1685-1695 (2006)
89EESarvesh H. Kulkarni, Dennis Sylvester: Power Distribution Techniques for Dual VDD Circuits. J. Low Power Electronics 2(2): 217-229 (2006)
2005
88EEMatthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown: Optimization objectives and models of variation for statistical gate sizing. ACM Great Lakes Symposium on VLSI 2005: 313-316
87EERobert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge: Total leakage optimization strategies for multi-level caches. ACM Great Lakes Symposium on VLSI 2005: 381-384
86EEHimanshu Kaul, Dennis Sylvester: A novel buffer circuit for energy efficient signaling in dual-VDD systems. ACM Great Lakes Symposium on VLSI 2005: 462-467
85EEKanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan: Achieving continuous VT performance in a dual VT process. ASP-DAC 2005: 393-398
84EEDongwoo Lee, David Blaauw, Dennis Sylvester: Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment. ASP-DAC 2005: 399-404
83EEMridul Agarwal, Kanak Agarwal, Dennis Sylvester, David Blaauw: Statistical modeling of cross-coupling effects in VLSI interconnects. ASP-DAC 2005: 503-506
82EEJie Yang, Luigi Capodieci, Dennis Sylvester: Advanced timing analysis based on post-OPC extraction of critical dimensions. DAC 2005: 359-364
81EEPuneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester: Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. DAC 2005: 365-368
80EEAshish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director: Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. DAC 2005: 535-540
79EERobert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge: Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage. DATE 2005: 650-651
78EEHimanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction. DATE 2005: 80-85
77 Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester: Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. ICCAD 2005: 1023-1028
76 Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov: Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. ICCAD 2005: 705-712
75EERahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif: Power-aware global signaling strategies. ISCAS (1) 2005: 604-607
74EEEric Karl, Dennis Sylvester, David Blaauw: Timing error correction techniques for voltage-scalable on-chip memories. ISCAS (4) 2005: 3563-3566
73EEBo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester: Analysis and mitigation of variability in subthreshold design. ISLPED 2005: 20-25
72EERajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif: An efficient surface-based low-power buffer insertion algorithm. ISPD 2005: 86-93
71EEHarmander Deogun, Dennis Sylvester, David Blaauw: Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate. ISQED 2005: 175-180
70EEPuneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: Performance Driven OPC for Mask Cost Reduction. ISQED 2005: 270-275
69EERahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown: Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. ISQED 2005: 284-290
68EEHarmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka: Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. ISQED 2005: 88-93
67EEYu-Shiang Lin, Dennis Sylvester: A New Asymmetric Skewed Buffer Design for Runtime Leakage Power Reduction. VLSI Design 2005: 824-827
66EERajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan: Modeling and Analysis of Parametric Yield under Power and Performance Constraints. IEEE Design & Test of Computers 22(4): 376-385 (2005)
65EEYu Cao, Xuejue Huang, Dennis Sylvester, Tsu-Jae King, Chenming Hu: Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design. IEEE Trans. VLSI Syst. 13(1): 158-162 (2005)
64EEHimanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy: Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses. IEEE Trans. VLSI Syst. 13(11): 1225-1238 (2005)
63EEBo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner: The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. IEEE Trans. VLSI Syst. 13(11): 1239-1252 (2005)
62EEAnup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar: Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits. IEEE Trans. VLSI Syst. 13(12): 1362-1375 (2005)
61EERajeev R. Rao, Harmander Deogun, David Blaauw, Dennis Sylvester: Bus encoding for total power reduction using a leakage-aware buffer configuration. IEEE Trans. VLSI Syst. 13(12): 1376-1383 (2005)
60EEYu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester: Switch-factor based loop RLC modeling for efficient timing analysis. IEEE Trans. VLSI Syst. 13(9): 1072-1078 (2005)
59EEDongwoo Lee, David Blaauw, Dennis Sylvester: Static leakage reduction through simultaneous V/sub t//T/sub ox/ and state assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1014-1029 (2005)
2004
58EEKanak Agarwal, Dennis Sylvester, David Blaauw: A simplified transmission-line based crosstalk noise model for on-chip RLC wiring. ASP-DAC 2004: 858-864
57EELuigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: Toward a methodology for manufacturability-driven design rule exploration. DAC 2004: 311-316
56EEPuneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester: Selective gate-length biasing for cost-effective runtime leakage control. DAC 2004: 327-330
55EEKanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula: Variational delay metrics for interconnect timing analysis. DAC 2004: 381-384
54EERajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Parametric yield estimation considering leakage variability. DAC 2004: 442-447
53EEAnup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar: Tradeoffs between date oxide leakage and delay for dual Tox circuits. DAC 2004: 761-766
52EEAshish Srivastava, Dennis Sylvester, David Blaauw: Statistical optimization of leakage power considering process variations using dual-Vth and sizing. DAC 2004: 773-778
51EEHarmander Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw: Leakage-and crosstalk-aware bus encoding for total power reduction. DAC 2004: 779-782
50EEAshish Srivastava, Dennis Sylvester, David Blaauw: Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. DAC 2004: 783-787
49EEBo Zhai, David Blaauw, Dennis Sylvester, Krisztián Flautner: Theoretical and practical limits of dynamic voltage scaling. DAC 2004: 868-873
48EEDongwoo Lee, Harmander Deogun, David Blaauw, Dennis Sylvester: Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization. DATE 2004: 494-499
47EEAshish Srivastava, Dennis Sylvester, David Blaauw: Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design. DATE 2004: 718-719
46EEAshish Srivastava, Dennis Sylvester: A general framework for probabilistic low-power design space exploration considering process variation. ICCAD 2004: 808-813
45EESaumil Shah, Kanak Agarwal, Dennis Sylvester: A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters. ICCD 2004: 138-143
44EEAnup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar: Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits. ICCD 2004: 228-233
43EERahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif: Approaches to run-time and standby mode leakage reduction in global buses. ISLPED 2004: 188-193
42EEHimanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy: Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. ISLPED 2004: 194-199
41EESarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester: A new algorithm for improved VDD assignment in low power dual VDD systems. ISLPED 2004: 200-205
40EEDesmond Kirkpatrick, Pete Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester: The great interconnect buffering debate: are you a chicken or an ostrich? ISPD 2004: 61
39EEPuneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester: Investigation of performance metrics for interconnect stack architectures. SLIP 2004: 23-29
38 Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 131-139 (2004)
37 Dongwoo Lee, David Blaauw, Dennis Sylvester: Gate oxide leakage current analysis and reduction for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 155-166 (2004)
36 Himanshu Kaul, Dennis Sylvester: Low-power on-chip communication based on transition-aware global signaling (TAGS). IEEE Trans. VLSI Syst. 12(5): 464-476 (2004)
35EESarvesh H. Kulkarni, Dennis Sylvester: High performance level conversion for dual VDD design. IEEE Trans. VLSI Syst. 12(9): 926-936 (2004)
34EEKanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driver output model for on-chip RLC transmission lines. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 128-136 (2004)
33EEAshish Srivastava, Dennis Sylvester: Minimizing total power by simultaneous V/sub dd//V/sub th/ assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 665-677 (2004)
32EEKanak Agarwal, Dennis Sylvester, David Blaauw: A simple metric for slew rate of RC circuits based on two circuit moments. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1346-1354 (2004)
2003
31 Dennis Sylvester, Dirk Stroobandt, Louis Scheffer, Payman Zarkesh-Ha: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings ACM 2003
30EEJan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang: Reshaping EDA for power. DAC 2003: 15
29EEPuneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. DAC 2003: 16-21
28EEDongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Analysis and minimization techniques for total leakage considering gate oxide leakage. DAC 2003: 175-180
27EEKanak Agarwal, Dennis Sylvester, David Blaauw: An effective capacitance based driver output model for on-chip RLC interconnects. DAC 2003: 376-381
26EERuchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni: Pushing ASIC performance in a power envelope. DAC 2003: 788-793
25EEKanak Agarwal, Dennis Sylvester, David Blaauw: Simple metrics for slew rate of RC circuits based on two circuit moments. DAC 2003: 950-953
24EEYu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester: Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis. ICCAD 2003: 848-854
23EEShidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester: Optimal Inductance for On-chip RLC Interconnections. ICCD 2003: 264-
22EERajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical estimation of leakage current considering inter- and intra-die process variation. ISLPED 2003: 84-89
21EEDongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design. ISQED 2003: 287-292
20EERobert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw: An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. ISVLSI 2003: 149-154
19EEYu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester: Improved a priori interconnect predictions and technology extrapolation in the GTX system. IEEE Trans. VLSI Syst. 11(1): 3-14 (2003)
18EETakashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu: Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 560-572 (2003)
2002
17EEHimanshu Kaul, Dennis Sylvester, David Blaauw: Active shields: a new approach to shielding global wires. ACM Great Lakes Symposium on VLSI 2002: 112-117
16EEKanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu: Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. ASP-DAC 2002: 77-86
15EEAshish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester: Modeling and analysis of leakage power considering within-die process variations. ISLPED 2002: 64-67
14EEHimanshu Kaul, Dennis Sylvester: Transition Aware Global Signaling (TAGS). ISQED 2002: 53-
13EEKanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driving point model for on-chip RLC interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 63-69
12EEHimanshu Kaul, Dennis Sylvester, David Blaauw: Active shielding of RLC global interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 98-104
11EEKanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu: Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. VLSI Design 2002: 77-
10EEYu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu: Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. IEEE Trans. VLSI Syst. 10(6): 799-805 (2002)
2001
9EEDennis Sylvester, Himanshu Kaul: Future Performance Challenges in Nanometer Design. DAC 2001: 3-8
8EEDennis Sylvester, Himanshu Kaul: Power-Driven Challenges in Nanometer Design. IEEE Design & Test of Computers 18(6): 12-22 (2001)
2000
7EEAndrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester: GTX: the MARCO GSRC technology extrapolation system. DAC 2000: 693-698
6 Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester: Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. ICCAD 2000: 56-61
5EEDennis Sylvester: Measurement techniques and interconnect estimation. SLIP 2000: 79-81
4EEDennis Sylvester, Kurt Keutzer: A global wiring paradigm for deep submicron design. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 242-252 (2000)
1999
3EEDennis Sylvester, Kurt Keutzer: Getting to the bottom of deep submicron II: a global wiring paradigm. ISPD 1999: 193-200
2 Dennis Sylvester, Kurt Keutzer: Rethinking Deep-Submicron Circuit Design. IEEE Computer 32(11): 25-33 (1999)
1998
1EEDennis Sylvester, Kurt Keutzer: Getting to the bottom of deep submicron. ICCAD 1998: 203-211

Coauthor Index

1Kanak Agarwal [11] [13] [16] [18] [23] [25] [27] [32] [34] [43] [45] [55] [58] [69] [75] [80] [83] [85] [92] [93] [96] [114] [115] [131]
2Mridul Agarwal [83] [92]
3Charles J. Alpert [72]
4Mark Anders [42] [64]
5Todd M. Austin [78] [117]
6Robert Bai [15] [20] [79] [87] [116]
7Murat R. Becer [121] [127]
8Kerry Bernstein [30] [95]
9Clive Bittlestone [106]
10David Blaauw (David T. Blaauw) [12] [13] [15] [17] [20] [21] [22] [23] [25] [27] [28] [30] [32] [34] [37] [38] [47] [48] [49] [50] [51] [52] [54] [55] [58] [59] [61] [63] [66] [71] [72] [73] [74] [76] [77] [78] [80] [83] [84] [85] [90] [92] [93] [94] [95] [97] [99] [100] [102] [103] [104] [105] [107] [112] [117] [118] [119] [120] [121] [122] [123] [124] [125] [127] [130] [131]
11Richard B. Brown [43] [68] [69] [75] [88] [98] [108] [109] [114] [132]
12Andres Bryant [95] [99]
13Andrew E. Caldwell [7]
14Yu Cao [6] [7] [10] [11] [16] [18] [19] [24] [60] [65]
15Luigi Capodieci [57] [82]
16Leland Chang [95]
17N. H. Chang [10]
18Gregory K. Chen [123]
19Kaviraj Chopra [77] [104] [105] [112] [121] [127] [130]
20Brian Cline [131]
21John M. Cohn [26]
22Koushik K. Das [95]
23Shidhartha Das [23]
24Harmander Deogun [48] [51] [61] [68] [71] [96] [98] [101]
25Anirudh Devgan [54] [66] [69] [85] [90]
26Stephen W. Director [80]
27Ronald G. Dreslinski [120]
28Krisztián Flautner [49] [63]
29Jerry Frenkil [30]
30Ravikishore Gandikota [121] [127]
31Joao Geada [121]
32Puneet Gupta [29] [39] [56] [57] [70] [81] [91] [111] [126] [133]
33Matthew R. Guthaus [88] [108] [109] [132]
34Wilfried Haensch [95]
35Scott Hanson [73] [95] [99] [100] [124] [125]
36Mark Horowitz [30]
37Chenming Hu [6] [10] [11] [16] [18] [19] [65]
38Xuejue Huang [6] [10] [19] [24] [60] [65]
39Vivek Joshi [97] [122] [131]
40T. Kachru [113]
41Andrew B. Kahng [6] [7] [19] [29] [39] [56] [57] [70] [81] [91] [111] [126] [133]
42Eric Karl [74] [107]
43Himanshu Kaul [8] [9] [12] [14] [17] [36] [42] [64] [75] [78] [86] [117] [119]
44Kurt Keutzer [1] [2] [3] [4]
45Taeho Kgil [79] [116]
46Nam Sung Kim [79] [87] [116] [123]
47Youngmin Kim [39] [81] [111] [126] [129] [133]
48Tsu-Jae King [65]
49Desmond Kirkpatrick [40]
50Farinaz Koushanfar [7]
51Ram Krishnamurthy [42] [64] [119]
52Sarvesh H. Kulkarni [20] [26] [35] [41] [89] [103] [110]
53David S. Kung [26]
54Wesley Kwong [20] [21] [28]
55Dongwoo Lee [21] [28] [37] [48] [59] [84] [94]
56Shen Lin [10]
57Yu-Shiang Lin [67] [128]
58Frank Liu [55]
59Hua Lu [7]
60Igor L. Markov [7] [19]
61Sudhakar Muddu [6]
62Trevor N. Mudge [78] [79] [87] [107] [116] [117] [120] [123]
63O. Sam Nakagawa [10]
64Sani R. Nassif [43] [55] [72] [75] [106]
65Wolfgang Nebel [30]
66Edward J. Nowak [95]
67Kevin J. Nowka [43] [68] [69] [96] [98] [101] [115]
68Michael Oliver [7] [19]
69Pete Osler [40]
70David Z. Pan (David Zhigang Pan) [26]
71Dusan Petranovic [129]
72Vijay Pitchumani [106]
73Ruchir Puri [26]
74Jan M. Rabaey [30]
75Riko Radojcic [106]
76Rahul M. Rao [43] [68] [69] [75] [114]
77Rajeev R. Rao [22] [38] [51] [54] [61] [66] [72] [90] [97] [102] [105] [112]
78N. Rodriguez [106]
79Takayasu Sakurai [30]
80Sachin S. Sapatnekar [44] [53] [62]
81Takashi Sato [11] [16] [18]
82Prashant Saxena [40]
83Louis Scheffer [31] [40]
84Robert M. Senger [98]
85Jae-sun Seo [118] [119]
86Mingoo Seok [124] [125]
87Saumil Shah [45] [76] [77] [80] [126] [130] [133]
88Dushyant Sharma [76]
89Puneet Sharma [56] [91]
90H. Singh [115]
91Prashant Singh [118]
92Ashish Srivastava [15] [20] [22] [26] [33] [38] [41] [46] [47] [50] [52] [76] [77] [80] [113] [130]
93Leon Stok [26]
94Dirk Stroobandt [6] [7] [19] [31]
95Anup Kumar Sultania [44] [53] [62]
96Natesan Venkateswaran [88]
97Sarma B. K. Vrudhula [55]
98Xinlin Wang [99]
99Weize Xie [10]
100Andrew Yang [30]
101Jie Yang [29] [57] [70] [82]
102Xiao-dong Yang [24] [60]
103Payman Zarkesh-Ha [31]
104Bo Zhai [49] [63] [73] [95] [99] [104] [120]
105Vladimir Zolotov [76] [88]

Colors in the list of coauthors

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Copyright © Thu Jun 5 07:42:39 2008 by Michael Ley (ley@uni-trier.de)