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Dennis Sylvester Vis

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*2009
154EEVineeth Veetil, Dennis Sylvester, David Blaauw, Saumil Shah, Steffen Rochel: Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence. DAC 2009: 154-159
153EEDavid Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David Blaauw, Dennis Sylvester: Vicis: a reliable network for unreliable silicon. DAC 2009: 812-817
152EEDavid Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David Blaauw: A highly resilient routing algorithm for fault-tolerant NoCs. DATE 2009: 21-26
151EERonald G. Dreslinski, David Fick, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Reconfigurable Multicore Server Processors for Low Power Operation. SAMOS 2009: 247-254
2008
150EEPuneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester: Investigation of diffusion rounding for post-lithography analysis. ASP-DAC 2008: 480-485
149EEMatthew R. Guthaus, Dennis Sylvester, Richard B. Brown: Clock tree synthesis with data-path sensitivity matching. ASP-DAC 2008: 498-503
148EEVineeth Veetil, Dennis Sylvester, David Blaauw: Efficient Monte Carlo based incremental statistical timing analysis. DAC 2008: 676-681
147EEVivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Leakage power reduction using stress-enhanced layouts. DAC 2008: 912-917
146EERavikishore Gandikota, David Blaauw, Dennis Sylvester: Modeling crosstalk in statistical static timing analysis. DAC 2008: 974-979
145EEJae-sun Seo, Igor L. Markov, Dennis Sylvester, David Blaauw: On the decreasing significance of large standard cells in technology mapping. ICCAD 2008: 116-121
144EEBrian Cline, Vivek Joshi, Dennis Sylvester, David Blaauw: STEEL: a technique for stress-enhanced standard cell library design. ICCAD 2008: 691-697
143EEKaviraj Chopra, Cheng Zhuo, David Blaauw, Dennis Sylvester: A statistical approach for full-chip gate-oxide reliability analysis. ICCAD 2008: 698-705
142EEYu-Shiang Lin, Scott Hanson, Fabio Albano, Carlos Tokunaga, Razi-Ul Haque, Kensall Wise, Ann Marie Sastry, David Blaauw, Dennis Sylvester: Low-voltage circuit design for widespread sensing applications. ISCAS 2008: 2558-2561
141EEHimanshu Kaul, Jae-sun Seo, Mark Anders, Dennis Sylvester, Ram Krishnamurthy: A robust alternate repeater technique for high performance busses in the multi-core era. ISCAS 2008: 372-375
140EECheng Zhuo, David Blaauw, Dennis Sylvester: Variation-aware gate sizing and clustering for post-silicon optimized circuits. ISLPED 2008: 105-110
139EEMingoo Seok, Dennis Sylvester, David Blaauw: Optimal technology selection for minimizing energy and variability in low voltage applications. ISLPED 2008: 9-14
138EEVivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Stress aware layout optimization. ISPD 2008: 168-174
137EEEric Karl, Dennis Sylvester, David Blaauw: Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures. ISQED 2008: 391-395
136EEVineeth Veetil, Dennis Sylvester, David Blaauw: Fast and Accurate Waveform Analysis with Current Source Models. ISQED 2008: 53-56
135EERonald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David Blaauw, Dennis Sylvester, Krisztián Flautner: Reconfigurable energy efficient near threshold cache architectures. MICRO 2008: 459-470
134EEEric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Multi-Mechanism Reliability Modeling and Management in Dynamic Systems. IEEE Trans. VLSI Syst. 16(4): 476-487 (2008)
133EEPrashant Singh, Jae-sun Seo, David Blaauw, Dennis Sylvester: Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect. IEEE Trans. VLSI Syst. 16(6): 673-677 (2008)
132EEAshish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw: A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 272-285 (2008)
131EEDennis Sylvester, Kanak Agarwal, Saumil Shah: Variability in nanometer CMOS: Impact, analysis, and minimization. Integration 41(3): 319-339 (2008)
2007
130EEYoungmin Kim, Dusan Petranovic, Dennis Sylvester: Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion. ASP-DAC 2007: 456-461
129EEYu-Shiang Lin, Dennis Sylvester: Runtime leakage power estimation technique for combinational circuits. ASP-DAC 2007: 660-665
128EERavikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer: Top-k Aggressors Sets in Delay Noise Analysis. DAC 2007: 174-179
127EEPuneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester: Line-End Shortening is Not Always a Failure. DAC 2007: 270-271
126EEMingoo Seok, Scott Hanson, Dennis Sylvester, David Blaauw: Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design. DAC 2007: 694-699
125EEScott Hanson, Mingoo Seok, Dennis Sylvester, David Blaauw: Nanometer Device Scaling in Subthreshold Circuits. DAC 2007: 700-705
124EEGregory K. Chen, David Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim: Yield-driven near-threshold SRAM design. ICCAD 2007: 660-666
123EEVivek Joshi, David Blaauw, Dennis Sylvester: Soft-edge flip-flops for improved timing yield: design and optimization. ICCAD 2007: 667-673
122EERavikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada: Victim alignment in crosstalk aware timing analysis. ICCAD 2007: 698-704
121EEBo Zhai, Ronald G. Dreslinski, David Blaauw, Trevor N. Mudge, Dennis Sylvester: Energy efficient near-threshold chip multi-processing. ISLPED 2007: 32-37
120EEJae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, Ram Krishnamurthy: A robust edge encoding technique for energy-efficient multi-cycle interconnect. ISLPED 2007: 68-73
119EEJae-sun Seo, Prashant Singh, Dennis Sylvester, David Blaauw: Self-Time Regenerators for High-Speed and Low-Power Interconnect. ISQED 2007: 621-626
118EERonald G. Dreslinski, Bo Zhai, Trevor N. Mudge, David Blaauw, Dennis Sylvester: An Energy Efficient Parallel Architecture Using Near Threshold Operation. PACT 2007: 175-188
117EEHimanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction CoRR abs/0710.4679: (2007)
116EERobert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge: Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage CoRR abs/0710.4794: (2007)
115EEH. Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka: Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. IEEE Trans. VLSI Syst. 15(11): 1215-1224 (2007)
114EEKanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown: Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. IEEE Trans. VLSI Syst. 15(6): 613-623 (2007)
113EEAshish Srivastava, T. Kachru, Dennis Sylvester: Low-Power-Design Space Exploration Considering Process Variation Using Robust Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 67-79 (2007)
112EERajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester: Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 468-479 (2007)
111EEPuneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester: Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1614-1624 (2007)
2006
110EESarvesh H. Kulkarni, Dennis Sylvester: Power distribution techniques for dual VDD circuits. ASP-DAC 2006: 838-843
109EEMatthew R. Guthaus, Dennis Sylvester, Richard B. Brown: Process-induced skew reduction in nominal zero-skew clock trees. ASP-DAC 2006: 84-89
108EEMatthew R. Guthaus, Dennis Sylvester, Richard B. Brown: Clock buffer and wire sizing using sequential programming. DAC 2006: 1041-1046
107EEEric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Reliability modeling and management in dynamic microprocessor-based systems. DAC 2006: 1057-1060
106EESani R. Nassif, Vijay Pitchumani, N. Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic: Variation-aware analysis: savior of the nanometer era? DAC 2006: 411-412
105EERajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester: An efficient static algorithm for computing the soft error rates of combinational circuits. DATE 2006: 164-169
104EEKaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester: A new statistical max operation for propagating skewness in statistical timing analysis. ICCAD 2006: 237-243
103EESarvesh H. Kulkarni, Dennis Sylvester, David Blaauw: A statistical framework for post-silicon tuning through body bias clustering. ICCAD 2006: 39-46
102EERajeev R. Rao, David Blaauw, Dennis Sylvester: Soft error reduction in combinational logic using gate resizing and flipflop selection. ICCAD 2006: 502-509
101EEHarmander Deogun, Dennis Sylvester, Kevin J. Nowka: Fine grained multi-threshold CMOS for enhanced leakage reduction. ISCAS 2006
100EEScott Hanson, Dennis Sylvester, David Blaauw: A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits. ISLPED 2006: 338-341
99EEScott Hanson, Bo Zhai, David Blaauw, Dennis Sylvester, Andres Bryant, Xinlin Wang: Energy optimality and variability in subthreshold design. ISLPED 2006: 363-365
98EEHarmander Deogun, Robert M. Senger, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka: A dual-VDD boosted pulsed bus technique for low power and low leakage operation. ISLPED 2006: 73-78
97EEVivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester: Logic SER Reduction through Flipflop Redesign. ISQED 2006: 611-616
96EEKanak Agarwal, Kevin J. Nowka, Harmander Deogun, Dennis Sylvester: Power Gating with Multiple Sleep Modes. ISQED 2006: 633-637
95EEScott Hanson, Bo Zhai, Kerry Bernstein, David Blaauw, Andres Bryant, Leland Chang, Koushik K. Das, Wilfried Haensch, Edward J. Nowak, Dennis Sylvester: Ultralow-voltage, minimum-energy CMOS. IBM Journal of Research and Development 50(4-5): 469-490 (2006)
94EEDennis Sylvester, David Blaauw, Eric Karl: ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon. IEEE Design & Test of Computers 23(6): 484-490 (2006)
93EEDongwoo Lee, David Blaauw, Dennis Sylvester: Runtime Leakage Minimization Through Probability-Aware Optimization. IEEE Trans. VLSI Syst. 14(10): 1075-1088 (2006)
92EEKanak Agarwal, Dennis Sylvester, David Blaauw: Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 892-901 (2006)
91EEKanak Agarwal, Mridul Agarwal, Dennis Sylvester, David Blaauw: Statistical interconnect metrics for physical-design optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1273-1288 (2006)
90EEPuneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester: Gate-length biasing for runtime-leakage control. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1475-1485 (2006)
89EERajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Analytical yield prediction considering leakage/performance correlation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1685-1695 (2006)
88EESarvesh H. Kulkarni, Dennis Sylvester: Power Distribution Techniques for Dual VDD Circuits. J. Low Power Electronics 2(2): 217-229 (2006)
2005
87EEMatthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown: Optimization objectives and models of variation for statistical gate sizing. ACM Great Lakes Symposium on VLSI 2005: 313-316
86EERobert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge: Total leakage optimization strategies for multi-level caches. ACM Great Lakes Symposium on VLSI 2005: 381-384
85EEHimanshu Kaul, Dennis Sylvester: A novel buffer circuit for energy efficient signaling in dual-VDD systems. ACM Great Lakes Symposium on VLSI 2005: 462-467
84EEKanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan: Achieving continuous VT performance in a dual VT process. ASP-DAC 2005: 393-398
83EEDongwoo Lee, David Blaauw, Dennis Sylvester: Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment. ASP-DAC 2005: 399-404
82EEMridul Agarwal, Kanak Agarwal, Dennis Sylvester, David Blaauw: Statistical modeling of cross-coupling effects in VLSI interconnects. ASP-DAC 2005: 503-506
81EEJie Yang, Luigi Capodieci, Dennis Sylvester: Advanced timing analysis based on post-OPC extraction of critical dimensions. DAC 2005: 359-364
80EEPuneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester: Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. DAC 2005: 365-368
79EEAshish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director: Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. DAC 2005: 535-540
78EERobert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge: Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage. DATE 2005: 650-651
77EEHimanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction. DATE 2005: 80-85
76 Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester: Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. ICCAD 2005: 1023-1028
75 Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov: Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. ICCAD 2005: 705-712
74EERahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif: Power-aware global signaling strategies. ISCAS (1) 2005: 604-607
73EEEric Karl, Dennis Sylvester, David Blaauw: Timing error correction techniques for voltage-scalable on-chip memories. ISCAS (4) 2005: 3563-3566
72EEBo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester: Analysis and mitigation of variability in subthreshold design. ISLPED 2005: 20-25
71EERajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif: An efficient surface-based low-power buffer insertion algorithm. ISPD 2005: 86-93
70EEHarmander Deogun, Dennis Sylvester, David Blaauw: Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate. ISQED 2005: 175-180
69EEPuneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: Performance Driven OPC for Mask Cost Reduction. ISQED 2005: 270-275
68EERahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown: Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. ISQED 2005: 284-290
67EEHarmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka: Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. ISQED 2005: 88-93
66EEYu-Shiang Lin, Dennis Sylvester: A New Asymmetric Skewed Buffer Design for Runtime Leakage Power Reduction. VLSI Design 2005: 824-827
65EERajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan: Modeling and Analysis of Parametric Yield under Power and Performance Constraints. IEEE Design & Test of Computers 22(4): 376-385 (2005)
64EEYu Cao, Xuejue Huang, Dennis Sylvester, Tsu-Jae King, Chenming Hu: Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design. IEEE Trans. VLSI Syst. 13(1): 158-162 (2005)
63EEHimanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy: Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses. IEEE Trans. VLSI Syst. 13(11): 1225-1238 (2005)
62EEBo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner: The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. IEEE Trans. VLSI Syst. 13(11): 1239-1252 (2005)
61EEAnup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar: Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits. IEEE Trans. VLSI Syst. 13(12): 1362-1375 (2005)
60EERajeev R. Rao, Harmander Deogun, David Blaauw, Dennis Sylvester: Bus encoding for total power reduction using a leakage-aware buffer configuration. IEEE Trans. VLSI Syst. 13(12): 1376-1383 (2005)
59EEYu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester: Switch-factor based loop RLC modeling for efficient timing analysis. IEEE Trans. VLSI Syst. 13(9): 1072-1078 (2005)
58EEDongwoo Lee, David Blaauw, Dennis Sylvester: Static leakage reduction through simultaneous V/sub t//T/sub ox/ and state assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1014-1029 (2005)
2004
57EEKanak Agarwal, Dennis Sylvester, David Blaauw: A simplified transmission-line based crosstalk noise model for on-chip RLC wiring. ASP-DAC 2004: 858-864
56EELuigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: Toward a methodology for manufacturability-driven design rule exploration. DAC 2004: 311-316
55EEPuneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester: Selective gate-length biasing for cost-effective runtime leakage control. DAC 2004: 327-330
54EEKanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula: Variational delay metrics for interconnect timing analysis. DAC 2004: 381-384
53EERajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Parametric yield estimation considering leakage variability. DAC 2004: 442-447
52EEAnup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar: Tradeoffs between date oxide leakage and delay for dual Tox circuits. DAC 2004: 761-766
51EEAshish Srivastava, Dennis Sylvester, David Blaauw: Statistical optimization of leakage power considering process variations using dual-Vth and sizing. DAC 2004: 773-778
50EEHarmander Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw: Leakage-and crosstalk-aware bus encoding for total power reduction. DAC 2004: 779-782
49EEAshish Srivastava, Dennis Sylvester, David Blaauw: Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. DAC 2004: 783-787
48EEBo Zhai, David Blaauw, Dennis Sylvester, Krisztián Flautner: Theoretical and practical limits of dynamic voltage scaling. DAC 2004: 868-873
47EEDongwoo Lee, Harmander Deogun, David Blaauw, Dennis Sylvester: Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization. DATE 2004: 494-499
46EEAshish Srivastava, Dennis Sylvester, David Blaauw: Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design. DATE 2004: 718-719
45EEAshish Srivastava, Dennis Sylvester: A general framework for probabilistic low-power design space exploration considering process variation. ICCAD 2004: 808-813
44EESaumil Shah, Kanak Agarwal, Dennis Sylvester: A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters. ICCD 2004: 138-143
43EEAnup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar: Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits. ICCD 2004: 228-233
42EERahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif: Approaches to run-time and standby mode leakage reduction in global buses. ISLPED 2004: 188-193
41EEHimanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy: Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. ISLPED 2004: 194-199
40EESarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester: A new algorithm for improved VDD assignment in low power dual VDD systems. ISLPED 2004: 200-205
39EEDesmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester: The great interconnect buffering debate: are you a chicken or an ostrich? ISPD 2004: 61
38EEPuneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester: Investigation of performance metrics for interconnect stack architectures. SLIP 2004: 23-29
37 Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 131-139 (2004)
36 Dongwoo Lee, David Blaauw, Dennis Sylvester: Gate oxide leakage current analysis and reduction for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 155-166 (2004)
35 Himanshu Kaul, Dennis Sylvester: Low-power on-chip communication based on transition-aware global signaling (TAGS). IEEE Trans. VLSI Syst. 12(5): 464-476 (2004)
34EESarvesh H. Kulkarni, Dennis Sylvester: High performance level conversion for dual VDD design. IEEE Trans. VLSI Syst. 12(9): 926-936 (2004)
33EEKanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driver output model for on-chip RLC transmission lines. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 128-136 (2004)
32EEAshish Srivastava, Dennis Sylvester: Minimizing total power by simultaneous V/sub dd//V/sub th/ assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 665-677 (2004)
31EEKanak Agarwal, Dennis Sylvester, David Blaauw: A simple metric for slew rate of RC circuits based on two circuit moments. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1346-1354 (2004)
2003
30 Dennis Sylvester, Dirk Stroobandt, Louis Scheffer, Payman Zarkesh-Ha: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings ACM 2003
29EEJan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang: Reshaping EDA for power. DAC 2003: 15
28EEPuneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang: A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. DAC 2003: 16-21
27EEDongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Analysis and minimization techniques for total leakage considering gate oxide leakage. DAC 2003: 175-180
26EEKanak Agarwal, Dennis Sylvester, David Blaauw: An effective capacitance based driver output model for on-chip RLC interconnects. DAC 2003: 376-381
25EERuchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni: Pushing ASIC performance in a power envelope. DAC 2003: 788-793
24EEKanak Agarwal, Dennis Sylvester, David Blaauw: Simple metrics for slew rate of RC circuits based on two circuit moments. DAC 2003: 950-953
23EEYu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester: Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis. ICCAD 2003: 848-854
22EEShidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester: Optimal Inductance for On-chip RLC Interconnections. ICCD 2003: 264-
21EERajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical estimation of leakage current considering inter- and intra-die process variation. ISLPED 2003: 84-89
20EEDongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design. ISQED 2003: 287-292
19EERobert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw: An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. ISVLSI 2003: 149-154
18EEYu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester: Improved a priori interconnect predictions and technology extrapolation in the GTX system. IEEE Trans. VLSI Syst. 11(1): 3-14 (2003)
17EETakashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu: Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 560-572 (2003)
2002
16EEHimanshu Kaul, Dennis Sylvester, David Blaauw: Active shields: a new approach to shielding global wires. ACM Great Lakes Symposium on VLSI 2002: 112-117
15EEAshish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester: Modeling and analysis of leakage power considering within-die process variations. ISLPED 2002: 64-67
14EEHimanshu Kaul, Dennis Sylvester: Transition Aware Global Signaling (TAGS). ISQED 2002: 53-
13EEKanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driving point model for on-chip RLC interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 63-69
12EEHimanshu Kaul, Dennis Sylvester, David Blaauw: Active shielding of RLC global interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 98-104
11EEKanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu: Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. VLSI Design 2002: 77-
10EEYu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu: Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. IEEE Trans. VLSI Syst. 10(6): 799-805 (2002)
2001
9EEDennis Sylvester, Himanshu Kaul: Future Performance Challenges in Nanometer Design. DAC 2001: 3-8
8EEDennis Sylvester, Himanshu Kaul: Power-Driven Challenges in Nanometer Design. IEEE Design & Test of Computers 18(6): 12-22 (2001)
2000
7EEAndrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester: GTX: the MARCO GSRC technology extrapolation system. DAC 2000: 693-698
6 Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester: Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. ICCAD 2000: 56-61
5EEDennis Sylvester: Measurement techniques and interconnect estimation. SLIP 2000: 79-81
4EEDennis Sylvester, Kurt Keutzer: A global wiring paradigm for deep submicron design. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 242-252 (2000)
1999
3EEDennis Sylvester, Kurt Keutzer: Getting to the bottom of deep submicron II: a global wiring paradigm. ISPD 1999: 193-200
2 Dennis Sylvester, Kurt Keutzer: Rethinking Deep-Submicron Circuit Design. IEEE Computer 32(11): 25-33 (1999)
1998
1EEDennis Sylvester, Kurt Keutzer: Getting to the bottom of deep submicron. ICCAD 1998: 203-211

Coauthor Index

1Kanak Agarwal [11] [13] [17] [22] [24] [26] [31] [33] [42] [44] [54] [57] [68] [74] [79] [82] [84] [91] [92] [96] [114] [115] [131] [138] [147]
2Mridul Agarwal [82] [91]
3Fabio Albano [142]
4Charles J. Alpert [71]
5Mark Anders [41] [63] [141]
6Todd M. Austin [77] [117]
7Robert Bai [15] [19] [78] [86] [116]
8Murat R. Becer [122] [128]
9Kerry Bernstein [29] [95]
10Valeria Bertacco [152] [153]
11Clive Bittlestone [106]
12David Blaauw (David T. Blaauw) [12] [13] [15] [16] [19] [20] [21] [22] [24] [26] [27] [29] [31] [33] [36] [37] [46] [47] [48] [49] [50] [51] [53] [54] [57] [58] [60] [62] [65] [70] [71] [72] [73] [75] [76] [77] [79] [82] [83] [84] [89] [91] [92] [93] [94] [95] [97] [99] [100] [102] [103] [104] [105] [107] [112] [117] [118] [119] [120] [121] [122] [123] [124] [125] [126] [128] [132] [133] [134] [135] [136] [137] [138] [139] [140] [142] [143] [144] [145] [146] [147] [148] [151] [152] [153] [154]
13Richard B. Brown [42] [67] [68] [74] [87] [98] [108] [109] [114] [149]
14Andres Bryant [95] [99]
15Andrew E. Caldwell [7]
16Yu Cao [6] [7] [10] [11] [17] [18] [23] [59] [64]
17Luigi Capodieci [56] [81]
18Leland Chang [95]
19N. H. Chang [10]
20Gregory K. Chen [124] [135] [152]
21Kaviraj Chopra [76] [104] [105] [112] [122] [128] [132] [143]
22Brian Cline [138] [144] [147]
23John M. Cohn [25]
24Koushik K. Das [95]
25Shidhartha Das [22]
26Andrew DeOrio [152] [153]
27Harmander Deogun [47] [50] [60] [67] [70] [96] [98] [101]
28Anirudh Devgan [53] [65] [68] [84] [89]
29Stephen W. Director [79]
30Ronald G. Dreslinski [118] [121] [135] [151]
31David Fick [151] [152] [153]
32Krisztián Flautner [48] [62] [135]
33Jerry Frenkil [29]
34Ravikishore Gandikota [122] [128] [146]
35Joao Geada [122]
36Puneet Gupta [28] [38] [55] [56] [69] [80] [90] [111] [127] [150]
37Matthew R. Guthaus [87] [108] [109] [149]
38Wilfried Haensch [95]
39Scott Hanson [72] [95] [99] [100] [125] [126] [142]
40Razi-Ul Haque [142]
41Mark Horowitz [29]
42Chenming Hu [6] [10] [11] [17] [18] [64]
43Jin Hu [153]
44Xuejue Huang [6] [10] [18] [23] [59] [64]
45Vivek Joshi [97] [123] [138] [144] [147]
46T. Kachru [113]
47Andrew B. Kahng [6] [7] [18] [28] [38] [55] [56] [69] [80] [90] [111] [127] [150]
48Eric Karl [73] [94] [107] [134] [137]
49Himanshu Kaul [8] [9] [12] [14] [16] [35] [41] [63] [74] [77] [85] [117] [120] [141]
50Kurt Keutzer [1] [2] [3] [4]
51Taeho Kgil [78] [116]
52Nam Sung Kim [78] [86] [116] [124]
53Youngmin Kim [38] [80] [111] [127] [130] [150]
54Tsu-Jae King [64]
55Desmond Kirkpatrick [39]
56Farinaz Koushanfar [7]
57Ram Krishnamurthy [41] [63] [120] [141]
58Sarvesh H. Kulkarni [19] [25] [34] [40] [88] [103] [110]
59David S. Kung [25]
60Wesley Kwong [19] [20] [27]
61Dongwoo Lee [20] [27] [36] [47] [58] [83] [93]
62Shen Lin [10]
63Yu-Shiang Lin [66] [129] [142]
64Frank Liu [54]
65Hua Lu [7]
66Igor L. Markov [7] [18] [145]
67Sudhakar Muddu [6]
68Trevor N. Mudge [77] [78] [86] [107] [116] [117] [118] [121] [124] [134] [135] [151]
69O. Sam Nakagawa [10]
70Sani R. Nassif [42] [54] [71] [74] [106]
71Wolfgang Nebel [29]
72Edward J. Nowak [95]
73Kevin J. Nowka [42] [67] [68] [96] [98] [101] [115]
74Michael Oliver [7] [18]
75Peter J. Osler [39]
76David Z. Pan (David Zhigang Pan) [25]
77Dusan Petranovic [130]
78Vijay Pitchumani [106]
79Ruchir Puri [25]
80Jan M. Rabaey [29]
81Riko Radojcic [106]
82Rahul M. Rao [42] [67] [68] [74] [114]
83Rajeev R. Rao [21] [37] [50] [53] [60] [65] [71] [89] [97] [102] [105] [112]
84Steffen Rochel [154]
85N. Rodriguez [106]
86Takayasu Sakurai [29]
87Sachin S. Sapatnekar [43] [52] [61]
88Ann Marie Sastry [142]
89Takashi Sato [11] [17]
90Prashant Saxena [39]
91Louis Scheffer [30] [39]
92Robert M. Senger [98]
93Jae-sun Seo [119] [120] [133] [141] [145]
94Mingoo Seok [125] [126] [139]
95Saumil Shah [44] [75] [76] [79] [127] [131] [132] [150] [154]
96Dushyant Sharma [75]
97Puneet Sharma [55] [90]
98H. Singh [115]
99Prashant Singh [119] [133]
100Ashish Srivastava [15] [19] [21] [25] [32] [37] [40] [45] [46] [49] [51] [75] [76] [79] [113] [132]
101Leon Stok [25]
102Dirk Stroobandt [6] [7] [18] [30]
103Anup Kumar Sultania [43] [52] [61]
104Carlos Tokunaga [142]
105Vineeth Veetil [136] [148] [154]
106Natesan Venkateswaran [87]
107Sarma B. K. Vrudhula [54]
108Xinlin Wang [99]
109Kensall Wise [142]
110Weize Xie [10]
111Andrew Yang [29]
112Jie Yang [28] [56] [69] [81]
113Xiao-dong Yang [23] [59]
114Payman Zarkesh-Ha [30]
115Bo Zhai [48] [62] [72] [95] [99] [104] [118] [121]
116Cheng Zhuo [140] [143]
117Vladimir Zolotov [75] [87]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)