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Ashish Srivastava Vis

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*2008
17EEAshish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw: A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 272-285 (2008)
16EEDavid Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer: Statistical Timing Analysis: From Basic Principles to State of the Art. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 589-607 (2008)
2007
15EEAshish Srivastava, T. Kachru, Dennis Sylvester: Low-Power-Design Space Exploration Considering Process Variation Using Robust Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 67-79 (2007)
2005
14EEAshish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director: Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. DAC 2005: 535-540
13 Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester: Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. ICCAD 2005: 1023-1028
12 Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov: Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. ICCAD 2005: 705-712
2004
11EEAshish Srivastava, Dennis Sylvester, David Blaauw: Statistical optimization of leakage power considering process variations using dual-Vth and sizing. DAC 2004: 773-778
10EEAshish Srivastava, Dennis Sylvester, David Blaauw: Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. DAC 2004: 783-787
9EEAshish Srivastava, Dennis Sylvester, David Blaauw: Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design. DATE 2004: 718-719
8EEAshish Srivastava, Dennis Sylvester: A general framework for probabilistic low-power design space exploration considering process variation. ICCAD 2004: 808-813
7EESarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester: A new algorithm for improved VDD assignment in low power dual VDD systems. ISLPED 2004: 200-205
6 Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 131-139 (2004)
5EEAshish Srivastava, Dennis Sylvester: Minimizing total power by simultaneous V/sub dd//V/sub th/ assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 665-677 (2004)
2003
4EERuchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni: Pushing ASIC performance in a power envelope. DAC 2003: 788-793
3EERajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical estimation of leakage current considering inter- and intra-die process variation. ISLPED 2003: 84-89
2EERobert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw: An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. ISVLSI 2003: 149-154
2002
1EEAshish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester: Modeling and analysis of leakage power considering within-die process variations. ISLPED 2002: 64-67

Coauthor Index

1Kanak Agarwal [14]
2Robert Bai [1] [2]
3David Blaauw (David T. Blaauw) [1] [2] [3] [6] [9] [10] [11] [12] [13] [14] [16] [17]
4Kaviraj Chopra [13] [16] [17]
5John M. Cohn [4]
6Stephen W. Director [14]
7T. Kachru [15]
8Sarvesh H. Kulkarni [2] [4] [7]
9David S. Kung [4]
10Wesley Kwong [2]
11David Z. Pan (David Zhigang Pan) [4]
12Ruchir Puri [4]
13Rajeev R. Rao [3] [6]
14Louis Scheffer [16]
15Saumil Shah [12] [13] [14] [17]
16Dushyant Sharma [12]
17Leon Stok [4]
18Dennis Sylvester [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [17]
19Vladimir Zolotov [12]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)