| * | 2009 |
|---|
| 3 | EE | Lerong Cheng,
Puneet Gupta,
Costas J. Spanos,
Kun Qian,
Lei He:
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability.
DAC 2009: 104-109 |
| 2005 |
|---|
| 2 | EE | Paul Friedberg,
Yu Cao,
Jason Cain,
Ruth Wang,
Jan M. Rabaey,
Costas J. Spanos:
Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization.
ISQED 2005: 516-521 |
| 1986 |
|---|
| 1 | EE | Costas J. Spanos,
Stephen W. Director:
Parameter Extraction for Statistical IC Process Characterization.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(1): 66-78 (1986) |
