| * | 1997 |
|---|
| 4 | EE | Tolga Soyata,
Eby G. Friedman,
James H. Mulligan Jr.:
Incorporating interconnect, register, and clock distribution delays into the retiming process.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 105-120 (1997) |
| 1995 |
|---|
| 3 | | Tolga Soyata,
Eby G. Friedman,
James H. Mulligan Jr.:
Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay.
ISCAS 1995: 1748-1751 |
| 1994 |
|---|
| 2 | EE | Tolga Soyata,
Eby G. Friedman:
Retiming with non-zero clock skew, variable register, and interconnect delay.
ICCAD 1994: 234-241 |
| 1993 |
|---|
| 1 | | Tolga Soyata,
Eby G. Friedman,
James H. Mulligan Jr.:
Integration of Clock Skew and Register Delays into a Retiming Algorithm.
ISCAS 1993: 1483-1486 |
