Debjit Sinha

2007
16	EE	Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou: Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design 2007: 875-880
15	EE	Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou: Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 447-455 (2007)
14	EE	Debjit Sinha, Hai Zhou, Narendra V. Shenoy: Advances in Computation of the Maximum of a Set of Gaussian Random Variables. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1522-1533 (2007)
2006
13	EE	Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou: Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. DATE 2006: 618-623
12	EE	Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou: A timing dependent power estimation framework considering coupling. ICCAD 2006: 401-407
11	EE	Debjit Sinha, Hai Zhou, Narendra V. Shenoy: Advances in Computation of the Maximum of a Set of Random Variables. ISQED 2006: 306-311
10	EE	Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou: Yield-Aware Cache Architectures. MICRO 2006: 15-25
9	EE	Debjit Sinha, Narendra V. Shenoy, Hai Zhou: Statistical Timing Yield Optimization by Gate Sizing. IEEE Trans. VLSI Syst. 14(10): 1140-1146 (2006)
8	EE	Debjit Sinha, Hai Zhou: Statistical Timing Analysis With Coupling. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2965-2975 (2006)
7	EE	Debjit Sinha, Hai Zhou: Gate-size optimization under timing constraints for coupling-noise reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1064-1074 (2006)
2005
6	EE	Debjit Sinha, Hai Zhou: Yield driven gate sizing for coupling-noise reduction under uncertainty. ASP-DAC 2005: 192-197
5		Debjit Sinha, Narendra V. Shenoy, Hai Zhou: Statistical gate sizing for timing yield optimization. ICCAD 2005: 1037-1041
4		Debjit Sinha, Hai Zhou: A unified framework for statistical timing analysis with coupling and multiple input switching. ICCAD 2005: 837-843
2004
3	EE	Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee: An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. FPGA 2004: 256
2	EE	Debjit Sinha, Hai Zhou: Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. ICCAD 2004: 14-19
1	EE	Debjit Sinha, Hai Zhou, Chris C. N. Chu: Optimal gate sizing for coupling-noise reduction. ISPD 2004: 176-181

Coauthor Index

1	Jonathan Adams	[10]
2	Prithviraj Banerjee (Prith Banerjee)	[3] [13] [15]
3	Shabbir H. Batterywala	[16]
4	Chris C. N. Chu (Chris Chong-Nuen Chu)	[1]
5	Yehea I. Ismail	[12]
6	DiaaEldin Khalil	[12]
7	Jianfeng Luo	[16]
8	Arindam Mallik	[13] [15]
9	Gokhan Memik	[10]
10	Serkan Ozdemir	[10]
11	Subramanian Rajagopalan	[16]
12	Sanghamitra Roy	[3]
13	Narendra V. Shenoy	[5] [9] [11] [14] [16]
14	Hai Zhou	[1] [2] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16]