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Deshanand P. Singh Vis

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*2007
17EEAndrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: Incremental placement for structured ASICs using the transportation problem. VLSI-SoC 2007: 172-177
16EEValavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown: Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. VLSI Syst. 15(8): 895-903 (2007)
15EEAndrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1196-1210 (2007)
14EEDeshanand P. Singh, Stephen Dean Brown: An area-efficient timing closure technique for FPGAs using Shannon's expansion. Integration 40(2): 167-173 (2007)
2006
13EEGordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown: Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD 2006: 135-142
12EEValavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown: Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP 2006: 3-8
2005
11EEAndrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: FPGA technology mapping: a study of optimality. DAC 2005: 427-432
10EEDeshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown: Incremental retiming for FPGA physical synthesis. DAC 2005: 433-438
9 Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: FPGA PLB Evaluation using Quantified Boolean Satisfiability. FPL 2005: 19-24
8 Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown: Post-Placement BDD-Based Decomposition for FPGAs. FPL 2005: 31-38
7EEAndrew C. Ling, Deshanand P. Singh, Stephen Dean Brown: FPGA Logic Synthesis Using Quantified Boolean Satisfiability. SAT 2005: 444-450
2003
6 Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown: Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. VLSI 2003: 28-33
5 Deshanand P. Singh, Stephen Dean Brown: An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. VLSI 2003: 41-50
2002
4EEDeshanand P. Singh, Stephen Dean Brown: Constrained clock shifting for field programmable gate arrays. FPGA 2002: 121-126
3EEDeshanand P. Singh, Stephen Dean Brown: Integrated retiming and placement for field programmable gate arrays. FPGA 2002: 67-76
2EEDeshanand P. Singh, Stephen Dean Brown: Incremental placement for layout driven optimizations on FPGAs. ICCAD 2002: 752-759
2001
1EEDeshanand P. Singh, Stephen Dean Brown: The case for registered routing switches in field programmable gate arrays. FPGA 2001: 161-169

Coauthor Index

1Terry P. Borer [6]
2Stephen Dean Brown [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17]
3Gordon R. Chiu [12] [13] [16]
4Andrew C. Ling [7] [9] [11] [15] [17]
5Valavan Manohararajah [8] [10] [12] [13] [16]

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)