| 2006 |
|---|
| 24 | EE | Sungjae Kim,
Eugene Shragowitz:
Iterative-Constructive Standard Cell Placer for High Speed and Low Power.
ICCD 2006 |
| 2003 |
|---|
| 23 | EE | Eugene Shragowitz,
Habib Youssef,
Bing Lu:
Iterative Converging Algorithms for Computing Bounds on Durations of Activities in Pert and Pert-Like Models.
J. Comb. Optim. 7(1): 5-22 (2003) |
| 2002 |
|---|
| 22 | EE | H. Chang,
Eugene Shragowitz,
Jian Liu,
Habib Youssef,
Bing Lu,
Suphachai Sutanthavibul:
Net criticality revisited: an effective method to improve timing in physical design.
ISPD 2002: 155-160 |
| 2001 |
|---|
| 21 | | Jian Liu,
Eugene Shragowitz,
Wei-Tek Tsai:
Combining Hierarchical Filtering, Fuzzy Logic, and Simulation with Software Agents for IP (Intellectual Property) Selection in Electronic Design.
International Journal on Artificial Intelligence Tools 10(3): 303-323 (2001) |
| 20 | EE | Bing Lu,
Jun Gu,
Xiao-Dong Hu,
Eugene Shragowitz:
Wire segmenting for buffer insertion based on RSTP-MSP.
Theor. Comput. Sci. 262(1): 257-267 (2001) |
| 1995 |
|---|
| 19 | EE | Eric Q. Kang,
Eugene Shragowitz:
Generic fuzzy logic CAD development tool.
ASP-DAC 1995 |
| 18 | EE | Jung-Yong Lee,
Eugene Shragowitz:
Technology mapping for FPGAs with complex block architectures by fuzzy logic techniques.
ASP-DAC 1995 |
| 17 | | Jun-Yong Lee,
Eugene Shragowitz:
Performance Driven Technology Mapper for FPGAs with Complex Logic Block Structures.
ISCAS 1995: 1219-1222 |
| 1994 |
|---|
| 16 | EE | Eric Q. Kang,
Rung-Bin Lin,
Eugene Shragowitz:
Fuzzy logic approach to VLSI placement.
IEEE Trans. VLSI Syst. 2(4): 489-501 (1994) |
| 1993 |
|---|
| 15 | EE | Jaebum Lee,
Eugene Shragowitz,
David Poli:
Bounds on net lengths for high-speed PCB.
ICCAD 1993: 73-76 |
| 14 | EE | Suphachai Sutanthavibul,
Eugene Shragowitz,
Rung-Bin Lin:
An adaptive timing-driven placement for high performance VLSIs.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1488-1498 (1993) |
| 1992 |
|---|
| 13 | EE | Rung-Bin Lin,
Eugene Shragowitz:
Fuzzy Logic Approach to Placement Problem.
DAC 1992: 153-158 |
| 12 | EE | Habib Youssef,
Eugene Shragowitz,
Suphachai Sutanthavibul:
Prelayout timing analysis of cell-based VLSI designs.
Computer-Aided Design 24(7): 367-379 (1992) |
| 1991 |
|---|
| 11 | EE | Suphachai Sutanthavibul,
Eugene Shragowitz:
Dynamic Prediction of Critical Paths and Nets for Constructive Timing-Driven Placement.
DAC 1991: 632-635 |
| 10 | | Habib Youssef,
Rung-Bin Lin,
Eugene Shragowitz:
Bounds on Net Delays for Physical Design of Fast Circuits.
VLSI 1991: 111-118 |
| 9 | EE | Suphachai Sutanthavibul,
Eugene Shragowitz,
J. Ben Rosen:
An analytical approach to floorplan design and optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(6): 761-769 (1991) |
| 1990 |
|---|
| 8 | EE | Suphachai Sutanthavibul,
Eugene Shragowitz,
J. Ben Rosen:
An Analytical Approach to Floorplan Design and Optimization.
DAC 1990: 187-192 |
| 7 | EE | Suphachai Sutanthavibul,
Eugene Shragowitz:
An Adaptive Timing-Driven Layout for High Speed VLSI.
DAC 1990: 90-95 |
| 6 | | Habib Youssef,
Eugene Shragowitz:
Timing Constraints for Correct Performance.
ICCAD 1990: 24-27 |
| 1988 |
|---|
| 5 | | Jong Lee,
Eugene Shragowitz,
Sartaj Sahni:
A Hypercube Algorithm for the 0/1 Knapsack Problem.
J. Parallel Distrib. Comput. 5(4): 438-456 (1988) |
| 1987 |
|---|
| 4 | | Jong Lee,
Sartaj Sahni,
Eugene Shragowitz:
A Hypecube Algorithm for the 0/1 Knapsack Problem.
ICPP 1987: 699-706 |
| 1986 |
|---|
| 3 | EE | Surendra Nahar,
Sartaj Sahni,
Eugene Shragowitz:
Simulated annealing and combinatorial optimization.
DAC 1986: 293-299 |
| 2 | EE | David E. Krekelberg,
Eugene Shragowitz,
Gerald E. Sobelman,
Li-Shin Lin:
Automated layout synthesis in the YASC silicon compiler.
DAC 1986: 447-453 |
| 1985 |
|---|
| 1 | EE | Surendra Nahar,
Sartaj Sahni,
Eugene Shragowitz:
Experiments with simulated annealing.
DAC 1985: 748-752 |
