| * | 2009 |
|---|
| 8 | EE | Yu Liu,
Masato Yoshioka,
Katsumi Homma,
Toshiyuki Shibuya:
Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit.
ASP-DAC 2009: 498-503 |
| 2008 |
|---|
| 7 | EE | Katsumi Homma,
Izumi Nitta,
Toshiyuki Shibuya:
Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysis.
ASP-DAC 2008: 292-297 |
| 6 | EE | Wanping Zhang,
Yi Zhu,
Wenjian Yu,
Ling Zhang,
Rui Shi,
He Peng,
Zhi Zhu,
Lew Chua-Eoan,
Rajeev Murgai,
Toshiyuki Shibuya,
Nuriyoki Ito,
Chung-Kuan Cheng:
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network.
DATE 2008: 537-540 |
| 2007 |
|---|
| 5 | EE | Wanping Zhang,
Ling Zhang,
Rui Shi,
He Peng,
Zhi Zhu,
Lew Chua-Eoan,
Rajeev Murgai,
Toshiyuki Shibuya,
Noriyuki Ito,
Chung-Kuan Cheng:
Fast power network analysis with multiple clock domains.
ICCD 2007: 456-463 |
| 2005 |
|---|
| 4 | EE | Chung-Kuan Cheng,
Steve Lin,
Andrew B. Kahng,
Keh-Jeng Chang,
Vijay Pitchumani,
Toshiyuki Shibuya,
Roberto Suaya,
Zhiping Yu,
Fook-Luen Heng,
Don MacMillen:
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?
ASP-DAC 2005 |
| 2003 |
|---|
| 3 | EE | Toshiyuki Shibuya,
Rajeev Murgai,
Tadashi Konno,
Kazuhiro Emi,
Kaoru Kawamura:
PDL: A New Physical Synthesis Methodology.
ISQED 2003: 348- |
| 1997 |
|---|
| 2 | EE | Jason Cong,
Honching Peter Li,
Sung Kyu Lim,
Toshiyuki Shibuya,
Dongmin Xu:
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering.
ICCAD 1997: 441-446 |
| 1990 |
|---|
| 1 | | Kaoru Kawamura,
T. Shindo,
Toshiyuki Shibuya,
H. Miwatari,
Y. Ohki:
Touch and Cross Router.
ICCAD 1990: 56-59 |
