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* | 2009 | |
---|---|---|

31 | EE | Stefan Schäckeler, Weijia Shang, Ruth Davis: Visualization of Procedural Abstraction. Electr. Notes Theor. Comput. Sci. 224: 27-39 (2009) |

2007 | ||

30 | EE | Stefan Schäckeler, Weijia Shang: Stack size reduction of recursive programs. CASES 2007: 48-52 |

29 | EE | Jun Zhang, Xiaoquan Yi, Nam Ling, Weijia Shang: Chroma Coding Efficiency Improvement with Context Adaptive Lagrange Multiplier (CALM). ISCAS 2007: 293-296 |

28 | EE | Maria Pantoja, Nam Ling, Weijia Shang: Coefficient Conversion for Transform Domain VC-1 TO H.264 Transcoding. SiPS 2007: 363-367 |

2004 | ||

27 | Radhika S. Grover, Shobha Krishnan, Weijia Shang, Qiang Li: Performance Trade-offs of DCT with Variable Length Carry Chains in FPGAs. PDPTA 2004: 442-448 | |

2003 | ||

26 | Srinivasan Subha, Weijia Shang: On Data Locality in Supernode Transformation. PDPTA 2003: 1635-1641 | |

2002 | ||

25 | EE | Radhika S. Grover, Weijia Shang, Qiang Li: A faster distributed arithmetic architecture for FPGAs. FPGA 2002: 31-39 |

24 | EE | Edin Hodzic, Weijia Shang: On Time Optimal Supernode Shape. IEEE Trans. Parallel Distrib. Syst. 13(12): 1220-1233 (2002) |

23 | EE | Radhika S. Grover, Weijia Shang, Qiang Li: Bit-level two's complement matrix multiplication. Integration 33(1-2): 3-21 (2002) |

2000 | ||

22 | EE | Radhika S. Grover, Weijia Shang, Qiang Li: A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers. FPL 2000: 422-431 |

1999 | ||

21 | Edin Hodzic, Weijia Shang: On Time Optimal Supernode Shape. PDPTA 1999: 2019-2026 | |

1998 | ||

20 | EE | Edin Hodzic, Weijia Shang: On Supernode Transformation with Minimized Total Running Time. IEEE Trans. Parallel Distrib. Syst. 9(5): 417-428 (1998) |

1996 | ||

19 | EE | Edin Hodzic, Weijia Shang: On Supernode Transformation with Minimized Total Running Time. ASAP 1996: 402-414 |

18 | Edin Hodzic, Weijia Shang: On Optimal Size and Shape of Supernode Transformations. ICPP, Vol. 3 1996: 25-34 | |

17 | Weijia Shang, Edin Hodzic, Zhigang Chen: On Uniformization of Affine Dependence Algorithms. IEEE Trans. Computers 45(7): 827-840 (1996) | |

1994 | ||

16 | EE | Margaret A. Schaar, Kemal Efe, Weijia Shang: Queueing performance analysis of co-scheduling in a pool of processors environment. International Conference on Supercomputing 1994: 313-322 |

15 | José A. B. Fortes, Benjamin W. Wah, Weijia Shang, Kumar N. Ganapathy: Algorithm-Specific Parallel Processing with Linear Processor Arrays. Advances in Computers 38: 197-245 (1994) | |

14 | EE | Weijia Shang, Matthew T. O'Keefe, José A. B. Fortes: On Loop Transformations for Generalized Cycle Shrinking. IEEE Trans. Parallel Distrib. Syst. 5(2): 193-204 (1994) |

1993 | ||

13 | Weijia Shang, Benjamin W. Wah: Dependence Analysis and Architecture Design for Bit-Level Algorithms. ICPP 1993: 30-38 | |

12 | Zhigang Chen, Weijia Shang: Mapping of Uniform Dependence Algorithm onto Fixed Size Processor Arrays. IPPS 1993: 804-809 | |

1992 | ||

11 | Zhenhui Yang, Weijia Shang, José A. B. Fortes: Conflict-Free Scheduling of Nested Loop Algorithms on Lower Dimensional Processor Arrays. IPPS 1992: 156-164 | |

10 | Zhigang Chen, Weijia Shang: On Uniformization of Affine Dependence Algorithms. SPDP 1992: 128-137 | |

9 | Weijia Shang, José A. B. Fortes: Independent Partitioning of Algorithms with Uniform Dependencies. IEEE Trans. Computers 41(2): 190-206 (1992) | |

8 | EE | Weijia Shang, José A. B. Fortes: On Time Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays. IEEE Trans. Parallel Distrib. Syst. 3(3): 350-363 (1992) |

1991 | ||

7 | Weijia Shang, Matthew T. O'Keefe, José A. B. Fortes: Generalized cycle shrinking. Algorithms and Parallel VLSI Architectures 1991: 131-144 | |

6 | Weijia Shang, Matthew T. O'Keefe, José A. B. Fortes: On Loop Transformations for Generalized Cycle Shrinking. ICPP (2) 1991: 132-141 | |

5 | Weijia Shang, José A. B. Fortes: Time Optimal Linear Schedules for Algorithms with Uniform Dependencies. IEEE Trans. Computers 40(6): 723-742 (1991) | |

1990 | ||

4 | Weijia Shang, José A. B. Fortes: Time-Optimal and Conflict-Free Mappings of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays. ICPP (1) 1990: 101-110 | |

1989 | ||

3 | EE | Weijia Shang, José A. B. Fortes: On the optimality of linear schedules. VLSI Signal Processing 1(3): 209-220 (1989) |

1988 | ||

2 | Weijia Shang, José A. B. Fortes: Independent Partitioning of Algorithms With Uniform Data Dependencies. ICPP (2) 1988: 26-33 | |

1 | Benjamin W. Wah, Mokhtar Aboelaze, Weijia Shang: Systematic Designs of Buffers in Macropipelines of Systolic Arrays. J. Parallel Distrib. Comput. 5(1): 1-25 (1988) |

1 | Mokhtar Aboelaze | [1] |

2 | Zhigang Chen | [10] [12] [17] |

3 | Ruth Davis | [31] |

4 | Kemal Efe | [16] |

5 | José A. B. Fortes | [2] [3] [4] [5] [6] [7] [8] [9] [11] [14] [15] |

6 | Kumar N. Ganapathy | [15] |

7 | Radhika S. Grover | [22] [23] [25] [27] |

8 | Edin Hodzic | [17] [18] [19] [20] [21] [24] |

9 | Shobha Krishnan | [27] |

10 | Qiang Li | [22] [23] [25] [27] |

11 | Nam Ling | [28] [29] |

12 | Matthew T. O'Keefe | [6] [7] [14] |

13 | Maria Pantoja | [28] |

14 | Margaret A. Schaar | [16] |

15 | Stefan Schäckeler | [30] [31] |

16 | Srinivasan Subha | [26] |

17 | Benjamin W. Wah | [1] [13] [15] |

18 | Zhenhui Yang | [11] |

19 | Xiaoquan Yi | [29] |

20 | Jun Zhang | [29] |