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Edwin Hsing-Mean Sha Vis

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*2009
159EECathy Qun Xu, Chun Jason Xue, Bessie C. Hu, Edwin Hsing-Mean Sha: Computation and data transfer co-scheduling for interconnection bus minimization. ASP-DAC 2009: 311-316
158 Meilin Liu, Edwin Hsing-Mean Sha, Chun Xue, Meikang Qiu: Loop Fusion Technique with Minimal Memory Cost via Retiming. CATA 2009: 92-98
157EEMeikang Qiu, Lei Zhang, Edwin Hsing-Mean Sha: ILP optimal scheduling for multi-module memory. CODES+ISSS 2009: 277-286
156EEChun Jason Xue, Guoliang Xing, Zhaohui Yuan, Zili Shao, Edwin Hsing-Mean Sha: Joint Sleep Scheduling and Mode Assignment in Wireless Cyber-Physical Systems. ICDCS Workshops 2009: 1-6
155EEMeikang Qiu, Hao Li, Edwin Hsing-Mean Sha: Heterogeneous real-time embedded software optimization considering hardware platform. SAC 2009: 1637-1641
154EEMeikang Qiu, Edwin Hsing-Mean Sha: Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
153EEKevin F. Chen, Edwin Hsing-Mean Sha, Si-Qing Zheng: Fast and noniterative scheduling in input-queued switches: Supporting QoS. Computer Communications 32(5): 834-846 (2009)
152EEChun Jason Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha: Optimizing parallelism for nested loops with iterational and instructional retiming. J. Embedded Computing 3(1): 29-37 (2009)
151EEMeikang Qiu, Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha: Energy minimization for heterogeneous wireless sensor networks. J. Embedded Computing 3(2): 109-117 (2009)
150EEMeikang Qiu, Minyi Guo, Meiqin Liu, Chun Jason Xue, Laurence Tianruo Yang, Edwin Hsing-Mean Sha: Loop scheduling and bank type assignment for heterogeneous multi-bank memory. J. Parallel Distrib. Comput. 69(6): 546-558 (2009)
2008
149EEChun Jason Xue, Edwin Hsing-Mean Sha, Zili Shao, Meikang Qiu: Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints. DATE 2008: 1202-1207
148EEMeikang Qiu, Jiande Wu, Jingtong Hu, Yi He, Edwin Hsing-Mean Sha: Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment. EUC (1) 2008: 192-198
147EEMeikang Qiu, Jiande Wu, Chun Jason Xue, Jingtong Hu, Wei-Che Tseng, Edwin Hsing-Mean Sha: Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory. FPL 2008: 459-462
146EEMeikang Qiu, Jing Deng, Edwin Hsing-Mean Sha: Failure Rate Minimization with Multiple Function Unit Scheduling for Heterogeneous WSNs. GLOBECOM 2008: 5213-5217
145 Meikang Qiu, Jiande Wu, Chun Jason Xue, Jingtong Hu, Wei-Che Tseng, Edwin Hsing-Mean Sha: QoS for Networked Heterogeneous Real-Time Embedded Systems. ISCA PDCCS 2008: 135-140
144EEChun Jason Xue, Zhaohui Yuan, Guoliang Xing, Zili Shao, Edwin Hsing-Mean Sha: Energy Efficient Operating Mode Assignment for Real-Time Tasks in Wireless Embedded Systems. RTCSA 2008: 237-246
143EEJingtong Hu, Chun Jason Xue, Meikang Qiu, Wei-Che Tseng, Cathy Qun Xu, Lei Zhang, Edwin Hsing-Mean Sha: Minimizing Transferred Data for Code Update on Wireless Sensor Network. WASA 2008: 349-360
142EEMeikang Qiu, Edwin Hsing-Mean Sha, Meilin Liu, Man Lin, Shaoxiong Hua, Laurence Tianruo Yang: Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP. J. Parallel Distrib. Comput. 68(4): 443-455 (2008)
141EEQingfeng Zhuge, Chun Jason Xue, Meikang Qiu, Jingtong Hu, Edwin Hsing-Mean Sha: Timing optimization via nest-loop pipelining considering code size. Microprocessors and Microsystems - Embedded Hardware Design 32(7): 351-363 (2008)
140EEYen-Kuang Chen, David W. Lin, John V. McCanny, Edwin Hsing-Mean Sha: Guest Editorial: Special Issue on Design and Programming of Signal Processors for Multimedia Communication. Signal Processing Systems 51(3): 207-208 (2008)
2007
139 Tei-Wei Kuo, Edwin Hsing-Mean Sha, Minyi Guo, Laurence Tianruo Yang, Zili Shao: Embedded and Ubiquitous Computing, International Conference, EUC 2007, Taipei, Taiwan, December 17-20, 2007, Proceedings Springer 2007
138EEMeikang Qiu, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha: Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems. DATE 2007: 1641-1646
137EEChun Xue, Zili Shao, Meilin Liu, Qingfeng Zhuge, Edwin Hsing-Mean Sha: Parallel Network Intrusion Detection on Reconfigurable Platforms. EUC 2007: 75-86
136EESu Te Lei, Kang Zhang, Edwin Hsing-Mean Sha: Applying Situation Awareness to Mobile Proactive Information Delivery. EUC Workshops 2007: 592-603
135EEMeikang Qiu, Edwin Hsing-Mean Sha: Energy-Aware Online Algorithm to Satisfy Sampling Rates with Guaranteed Probability for Sensor Applications. HPCC 2007: 156-167
134EEMeng Wang, Zili Shao, Chun Xue, Edwin Hsing-Mean Sha: Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors. RTCSA 2007: 12-19
133EEBin Xiao, Jiannong Cao, Zili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha: Analysis and algorithms design for the partition of large-scale adaptive mobile wireless networks. Computer Communications 30(8): 1899-1912 (2007)
132EEKevin F. Chen, Edwin Hsing-Mean Sha: Universal Routing and Performance Assurance for Distributed Networks. Journal of Interconnection Networks 8(1): 1-28 (2007)
131EEMeikang Qiu, Zhiping Jia, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha: Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP. VLSI Signal Processing 46(1): 55-73 (2007)
130EEChun Xue, Zili Shao, Edwin Hsing-Mean Sha: Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping. VLSI Signal Processing 47(2): 153-167 (2007)
2006
129 Edwin Hsing-Mean Sha, Sung-Kook Han, Cheng-Zhong Xu, Moon-hae Kim, Laurence Tianruo Yang, Bin Xiao: Embedded and Ubiquitous Computing, International Conference, EUC 2006, Seoul, Korea, August 1-4, 2006, Proceedings Springer 2006
128EEMei Kang Qiu, Chun Xue, Qingfeng Zhuge, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha: Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability. ASAP 2006: 178-181
127EEMei Kang Qiu, Chun Xue, Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha: Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network. EUC 2006: 25-34
126EEChun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha: Loop Striping: Maximize Parallelism for Nested Loops. EUC 2006: 405-414
125EEChun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha: Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture. ICPADS (1) 2006: 375-382
124 Meilin Liu, Chun Xue, Edwin Hsing-Mean Sha: Optimizing Timing and Code Size Using Maximum Direct Loop Fusion. ISCA PDCS 2006: 38-43
123EEZili Shao, Bin Xiao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha: Loop scheduling with timing and switching-activity minimization for VLIW DSP. ACM Trans. Design Autom. Electr. Syst. 11(1): 165-185 (2006)
122EEZili Shao, Chun Xue, Qingfeng Zhuge, Mei Kang Qiu, Bin Xiao, Edwin Hsing-Mean Sha: Security Protection and Checking for Embedded System Integration against Buffer Overflow Attacks via Hardware/Software. IEEE Trans. Computers 55(4): 443-453 (2006)
121EEChantana Chantrapornchai, Wanlop Surakampontorn, Edwin Hsing-Mean Sha: Design Exploration With Imprecise Latency and Register Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2650-2662 (2006)
120EETimothy W. O'Neil, Edwin Hsing-Mean Sha: Time-constrained loop scheduling with minimal resources. J. Embedded Computing 2(1): 103-117 (2006)
119EEKevin F. Chen, Edwin Hsing-Mean Sha: The fat-stack and universal routing in interconnection networks. J. Parallel Distrib. Comput. 66(5): 705-715 (2006)
118EEZili Shao, Jiannong Cao, Keith C. C. Chan, Chun Xue, Edwin Hsing-Mean Sha: Hardware/software optimization for array & pointer boundary checking against buffer overflow attacks. J. Parallel Distrib. Comput. 66(9): 1129-1136 (2006)
117EEQingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, Meikang Qiu, Edwin Hsing-Mean Sha: Design optimization and space minimization considering timing and code size via retiming and unfolding. Microprocessors and Microsystems 30(4): 173-183 (2006)
2005
116EEZili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha: High-level synthesis for DSP applications using heterogeneous functional units. ASP-DAC 2005: 302-304
115EEChun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha: Iterational retiming: maximize iteration-level parallelism for nested loops. CODES+ISSS 2005: 309-314
114EEMeilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Mei Kang Qiu, Edwin Hsing-Mean Sha: Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs. EUC 2005: 121-130
113EEChun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha: Optimizing Nested Loops with Iterational and Instructional Retiming. EUC 2005: 164-173
112EEEdwin Hsing-Mean Sha: Parallel Embedded Systems: Optimizations and Challenges. EUC 2005: 2
111 Timothy W. O'Neil, Edwin Hsing-Mean Sha: Static Scheduling of Split-Node Data-Flow Graphs. IASTED PDCS 2005: 125-130
110 Mei Kang Qiu, Meilin Liu, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Zili Shao: Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems. IASTED PDCS 2005: 295-300
109EEBin Xiao, Wei Chen, Yanxiang He, Edwin Hsing-Mean Sha: An Active Detecting Method Against SYN Flooding Attack. ICPADS (1) 2005: 709-715
108EEYing Chen, Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha: Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems. ICPADS (2) 2005: 2-6
107EEKevin F. Chen, Edwin Hsing-Mean Sha, Bin Xiao: Universal Routing in Distributed Networks. ICPADS (2) 2005: 555-559
106 Kevin F. Chen, Meilin Liu, Edwin Hsing-Mean Sha: A Feasible Baseline Architecture for Building and Evaluating Distributed Systems. ISCA PDCS 2005: 185-190
105 Meilin Liu, Zili Shao, Chun Xue, Kevin F. Chen, Edwin Hsing-Mean Sha: Multi-level Loop Fusion with Minimal Code Size. ISCA PDCS 2005: 348-
104EEMeilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Meikang Qiu, Edwin Hsing-Mean Sha: Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size. ISPAN 2005: 126-131
103EEKevin F. Chen, Edwin Hsing-Mean Sha, S. Q. Zheng: A Fast Noniterative Scheduler for Input-Queued Switches with Unbuffered Crossbars. ISPAN 2005: 230-235
102EEZili Shao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Bin Xiao: Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software. ITCC (1) 2005: 780-785
101EEZili Shao, Qingfeng Zhuge, Chun Xue, Edwin Hsing-Mean Sha: Efficient Assignment and Scheduling for Heterogeneous DSP Systems. IEEE Trans. Parallel Distrib. Syst. 16(6): 516-525 (2005)
100EETimothy W. O'Neil, Edwin Hsing-Mean Sha: Combining Extended Retiming and Unfolding for Rate-Optimal Graph Transformation. VLSI Signal Processing 39(3): 273-293 (2005)
2004
99EEZili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, Edwin Hsing-Mean Sha: Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications. ASAP 2004: 224-234
98EEChantana Chantrapornchai, Wanlop Surakumpolthorn, Edwin Hsing-Mean Sha: Design Exploration Framework Under Impreciseness Based on Register-Constrained Inclusion Scheduling. ASIAN 2004: 78-92
97EEMeilin Liu, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha: General loop fusion technique for nested loops considering timing and code size. CASES 2004: 190-201
96EEChantana Chantrapornchai, Wanlop Surakumpolthorn, Edwin Hsing-Mean Sha: Efficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints. EUC 2004: 259-270
95EEZili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha, Bin Xiao: Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures. EUC 2004: 53-63
94EEChun Xue, Zili Shao, Edwin Hsing-Mean Sha, Bin Xiao: Optimizing Address Assignment for Scheduling Embedded DSPs. EUC 2004: 64-73
93EEBin Xiao, Jiannong Cao, Edwin Hsing-Mean Sha: Maintaining Comprehensive Resource Availability in P2P Networks. GCC 2004: 543-550
92EEQingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha: Timing Optimization of Nested Loops Considering Code Size for DSP Applications. ICPP 2004: 475-482
91EEZili Shao, Qingfeng Zhuge, Yi He, Chun Xue, Meilin Liu, Edwin Hsing-Mean Sha: Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units. IPDPS 2004
90 Kevin F. Chen, Edwin Hsing-Mean Sha: The Fat-Stack and Universal Routing in Interconnection Networks. ISCA PDCS 2004: 321-326
89 Meilin Liu, Qingfeng Zhuge, Zili Shao, Kevin F. Chen, Edwin Hsing-Mean Sha: Loop Fusion via Retiming for DSP Applications. ISCA PDCS 2004: 403-408
88EEBin Xiao, Jiannong Cao, Qingfeng Zhuge, Yi He, Edwin Hsing-Mean Sha: Approximation Algorithms Design for Disk Partial Covering Problem. ISPAN 2004: 104-110
87EEBin Xiao, Jiannong Cao, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha: Dynamic Update of Shortest Path Tree in OSPF. ISPAN 2004: 18-23
86EEZili Shao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Bin Xiao: Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks. ITCC (1) 2004: 409-413
85 Bin Xiao, Qingfeng Zhuge, Edwin Hsing-Mean Sha: Efficient Algorithms for Dynamic Update of Shortest Path Tree in Networking. I. J. Comput. Appl. 11(1): 60-75 (2004)
84EEZili Shao, Qingfeng Zhuge, Youtao Zhang, Edwin Hsing-Mean Sha: Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors. IJHPCN 1(1/2/3): 4-16 (2004)
83EEDavid R. Surma, Edwin Hsing-Mean Sha, Nelson L. Passos: Communication Scheduling With Re-Routing Based On Static And Hybrid Techniques. Journal of Circuits, Systems, and Computers 13(5): 1039-1064 (2004)
2003
82EEZili Shao, Qingfeng Zhuge, Yi He, Edwin Hsing-Mean Sha: Defending Embedded Systems Against Buffer Overflow via Hardware/Software. ACSAC 2003: 352-363
81EEQingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-Mean Sha: Design space minimization with timing and code size optimization for embedded DSP. CODES+ISSS 2003: 144-149
80 Cathy Qun Xu, Youtao Zhang, Edwin Hsing-Mean Sha: Application-Specific Interconnection Network Design in Clustered DSP Processors. ISCA PDCS 2003: 69-75
79 Bin Xiao, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha: Design and Analysis of Improved Shortest Path Tree Update for Network Routing. ISCA PDCS 2003: 82-87
78EEZili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai: Loop scheduling for minimizing schedule length and switching activities. ISCAS (5) 2003: 109-112
77EEQingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai: An Integrated Framework of Design Optimization and Space Minimization for DSP applications. ISCAS (5) 2003: 601-604
76EEQingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha: Code size reduction technique and implementation for software-pipelined DSP applications. ACM Trans. Embedded Comput. Syst. 2(4): 590-613 (2003)
75 Edwin Hsing-Mean Sha, Timothy W. O'Neil, Nelson L. Passos: Efficient Polynomial-Time Nested Loop Fusion with Full Parallelism. I. J. Comput. Appl. 10(1): 9-24 (2003)
2002
74EETimothy W. O'Neil, Edwin Hsing-Mean Sha: Minimizing resources in a repeating schedule for a split-node data-flow graph. ACM Great Lakes Symposium on VLSI 2002: 136-141
73 Bin Xiao, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai: Analysis and Algorithms for Partitioning of Large-scale Adaptive Mobile Networks. IASTED PDCS 2002: 302-308
72 Timothy W. O'Neil, Edwin Hsing-Mean Sha: Unfolding a Split-node Data-flow Graph. IASTED PDCS 2002: 712-717
71EEQingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha: Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications. ICPP 2002: 613-620
70EEQingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha: Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP. IPDPS 2002
69EEQingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha: Performance optimization of multiple memory architectures for DSP. ISCAS (5) 2002: 469-472
68EEBin Xiao, Zili Shao, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Qingfeng Zhuge: Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops. ISSS 2002: 144-149
2001
67 Edwin Hsing-Mean Sha: Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, August 8-10, 2001, Richardson, Texas, USA ISCA 2001
66EEZhong Wang, Edwin Hsing-Mean Sha, Yuke Wang: Optimal partitioning and balanced scheduling with the maximal overlap of data footprints. ACM Great Lakes Symposium on VLSI 2001: 31-36
65EEZhong Wang, Edwin Hsing-Mean Sha, Xiaobo Hu: Combined partitioning and data padding for scheduling multiple loop nests. CASES 2001: 67-75
64 Timothy W. O'Neil, Edwin Hsing-Mean Sha: On Retiming Synchronous Data-Flow Graphs. ISCA PDCS 2001: 103-108
63 Bin Xiao, Qingfeng Zhuge, Edwin Hsing-Mean Sha: Efficient Update of Shortest Path Algorithms for Network Routing. ISCA PDCS 2001: 315-320
62 Yingtao Jiang, Yuke Wang, Edwin Hsing-Mean Sha: Distributed Scaling Algorithm for FFT Computation Using Fixed-Point Arithmetic. ISCA PDCS 2001: 490-495
61 Zhong Wang, Qingfeng Zhuge, Edwin Hsing-Mean Sha: Scheduling and partitioning for multiple loop nests. ISSS 2001: 183-188
60EEXiaobo Sharon Hu, Tao Zhou, Edwin Hsing-Mean Sha: Estimating probabilistic timing performance for real-time embedded systems. IEEE Trans. VLSI Syst. 9(6): 833-844 (2001)
59EEZhong Wang, Timothy W. O'Neil, Edwin Hsing-Mean Sha: Minimizing Average Schedule Length under Memory Constraints by Optimal Partitioning and Prefetching. VLSI Signal Processing 27(3): 215-233 (2001)
2000
58EEVirgil Andronache, Edwin Hsing-Mean Sha, Nelson L. Passos: Design and analysis of efficient application-specific on-line page replacement techniques. ACM Great Lakes Symposium on VLSI 2000: 123-128
57EEChantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Hu: Efficient algorithms for acceptable design exploration. ACM Great Lakes Symposium on VLSI 2000: 139-142
56EEZhong Wang, Michael Kirkpatrick, Edwin Hsing-Mean Sha: Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications. DAC 2000: 540-545
55EEJiangfeng Ding, Jon C. Furgeson, Edwin Hsing-Mean Sha: Application Specific Image Compression for Virtual Conferencing. ITCC 2000: 48-53
54EESissades Tongsima, Edwin Hsing-Mean Sha, Chantana Chantrapornchai, David R. Surma, Nelson L. Passos: Probabilistic Loop Scheduling for Applications with Uncertain Execution Time. IEEE Trans. Computers 49(1): 65-80 (2000)
53EEFei Chen, Timothy W. O'Neil, Edwin Hsing-Mean Sha: Optimizing Overall Loop Schedules Using Prefetching and Partitioning. IEEE Trans. Parallel Distrib. Syst. 11(6): 604-614 (2000)
52EEDavid R. Surma, Edwin Hsing-Mean Sha: Communication Reduction in Multiple Multicasts Based on Hybrid Static-Dynamic Scheduling. IEEE Trans. Parallel Distrib. Syst. 11(9): 865-878 (2000)
51EEChantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Sharon Hu: Efficient design exploration based on module utility selection. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 19-29 (2000)
50EEChantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Sharon Hu: Efficient module selections for finding highly acceptable designs based on inclusion scheduling. Journal of Systems Architecture 46(11): 1047-1071 (2000)
49EESissades Tongsima, Timothy W. O'Neil, Chantana Chantrapornchai, Edwin Hsing-Mean Sha: Properties and Algorithms for Unfolding of Probabilistic Data-Flow Graphs. VLSI Signal Processing 25(3): 215-233 (2000)
1999
48EEChantana Chantrapornchai, Sissades Tongsima, Edwin Hsing-Mean Sha: Rapid Prototyping Techniques for Fuzzy Controllers. ASIAN 1999: 37-49
47EETao Zhou, Xiaobo Sharon Hu, Edwin Hsing-Mean Sha: A probabilistic performance metric for real-time system design. CODES 1999: 90-94
46EEChantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Sharon Hu: Efficient Algorithms for Finding Highly Acceptable Designs Based on Module-Utility Selections. Great Lakes Symposium on VLSI 1999: 128-131
45EEFei Chen, Edwin Hsing-Mean Sha: Loop Scheduling and Partitions for Hiding Memory Latencies. ISSS 1999: 64-70
1998
44EEKaisheng Wang, Ted Zhihong Yu, Edwin Hsing-Mean Sha: RCRS: A Framework for Loop Scheduling with Limited Number of Registers. Great Lakes Symposium on VLSI 1998: 386-391
43EEYi Tian, Edwin Hsing-Mean Sha, Chantana Chantrapornchai, Peter M. Kogge: Optimizing Data Scheduling on Processor-in-Memory Arrays. IPPS/SPDP 1998: 57-61
42EESissades Tongsima, Chantana Chantrapornchai, Edwin Hsing-Mean Sha: Probabilistic Loop Scheduling Considering Communication Overhead. JSSPP 1998: 158-179
41EEAnantha Chandrakasan, Edwin Hsing-Mean Sha: Special Section on Low-Power Electronics and Design. IEEE Trans. VLSI Syst. 6(4): 518-519 (1998)
40EENelson L. Passos, Edwin Hsing-Mean Sha: Scheduling of uniform multidimensional systems under resource constraints. IEEE Trans. VLSI Syst. 6(4): 719-730 (1998)
39EESissades Tongsima, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Nelson L. Passos: Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling. VLSI Signal Processing 18(2): 111-123 (1998)
1997
38EESissades Tongsima, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Nelson L. Passos: Scheduling with Confidence for Probabilistic Data-flow Graphs. Great Lakes Symposium on VLSI 1997: 150-155
37EETed Zhihong Yu, Edwin Hsing-Mean Sha, Nelson L. Passos, Roy Dz-Ching Ju: Algorithm and Hardware Support for Branch Anticipation. Great Lakes Symposium on VLSI 1997: 163-
36EESissades Tongsima, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Nelson L. Passos: Probabilistic Rotation: Scheduling Graphs with Uncertain Execution Time. ICPP 1997: 292-
35EEDavid R. Surma, Edwin Hsing-Mean Sha: Hybrid static-dynamic communication scheduling for parallel systems. SAC 1997: 374-379
34EELiang-Fang Chao, Edwin Hsing-Mean Sha: Scheduling Data-Flow Graphs via Retiming and Unfolding. IEEE Trans. Parallel Distrib. Syst. 8(12): 1259-1267 (1997)
33EENelson L. Passos, Edwin Hsing-Mean Sha, Liang-Fang Chao: Multidimensional interleaving for synchronous circuit design optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 16(2): 146-159 (1997)
32EELiang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Mean Sha: Rotation scheduling: a loop pipelining algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 229-239 (1997)
1996
31EEDavid R. Surma, Edwin Hsing-Mean Sha: Static Communication Scheduling for Minimizing Collisions in Application Specific Parallel Systems. ASAP 1996: 240-249
30EEMichael Sheliga, Nelson L. Passos, Edwin Hsing-Mean Sha: Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications. CODES 1996: 18-27
29EEChantana Chantrapornchai, Sissades Tongsima, Edwin Hsing-Mean Sha: Rapid Prototyping for Fuzzy Systems. Great Lakes Symposium on VLSI 1996: 234-239
28EENelson L. Passos, Edwin Hsing-Mean Sha: A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization. Great Lakes Symposium on VLSI 1996: 66-71
27EENelson L. Passos, Edwin Hsing-Mean Sha: Synthesis of Multi-Dimensional Applications in VHDL. ICCD 1996: 530-
26 Edwin Hsing-Mean Sha, Chenhua Lang, Nelson L. Passos: Polynomial-Time Nested Loop Fusion with Full Parallelism. ICPP, Vol. 3 1996: 9-16
25 Qingyan Wang, Nelson L. Passos, Edwin Hsing-Mean Sha: Optimal Data Scheduling for Uniform Multidimensional Applications. IEEE Trans. Computers 45(12): 1439-1444 (1996)
24EENelson L. Passos, Edwin Hsing-Mean Sha: Achieving Full Parallelism Using Multidimensional Retiming. IEEE Trans. Parallel Distrib. Syst. 7(11): 1150-1163 (1996)
23EEMichael Sheliga, Edwin Hsing-Mean Sha: Hardware/Software co-design with the HMS framework. VLSI Signal Processing 13(1): 37-56 (1996)
1995
22EEHai Zhao, Nicole Marie Sabine, Edwin Hsing-Mean Sha: Improving self-timed pipeline ring performance through the addition of buffer loops. Great Lakes Symposium on VLSI 1995: 218-223
21EEMichael Sheliga, Edwin Hsing-Mean Sha: Bus minimization and scheduling of multi-chip systems. Great Lakes Symposium on VLSI 1995: 40-45
20EENelson L. Passos, Edwin Hsing-Mean Sha: Push-up scheduling: Optimal polynomial-time resource constrained scheduling for multi-dimensional applications. ICCAD 1995: 588-591
19EENelson L. Passos, Edwin Hsing-Mean Sha, Liang-Fang Chao: Multi-dimensional interleaving for time-and-memory design optimization. ICCD 1995: 440-445
18 Nelson L. Passos, Edwin Hsing-Mean Sha, Liang-Fang Chao: Memory Efficient Fully Parallel Nested Loop Pipelining. ICPP (2) 1995: 182-185
17 Sissades Tongsima, Nelson L. Passos, Edwin Hsing-Mean Sha: Architecture-Dependent Loop Scheduling via Communication-Sensitive Remapping. ICPP (2) 1995: 97-104
16EELiang-Fang Chao, Edwin Hsing-Mean Sha: Static scheduling for synthesis of DSP algorithms on various models. VLSI Signal Processing 10(3): 207-223 (1995)
1994
15EENelson L. Passos, Edwin Hsing-Mean Sha, Steven C. Bass: Loop Pipelining for Scheduling Multi-Dimensional Systems via Rotation. DAC 1994: 485-490
14 Sissades Tongsima, Nelson L. Passos, Edwin Hsing-Mean Sha: Communication Sensitive Rotation Scheduling. ICCD 1994: 150-153
13 Nelson L. Passos, Edwin Hsing-Mean Sha: Full Parallelism in Uniform Nested Loops Using Multi-Dimensional Retiming. ICPP 1994: 130-133
12 Nelson L. Passos, Edwin Hsing-Mean Sha, Steven C. Bass: Schedule-Based Multi-Dimensional Retiming on Data Flow Graphs. IPPS 1994: 195-199
11 Nelson L. Passos, Edwin Hsing-Mean Sha, Steven C. Bass: Partitioning and Retiming of Multi-Dimensional Systems. ISCAS 1994: 227-230
10 Liang-Fang Chao, Edwin Hsing-Mean Sha: Retiming and Clock Skew for Synchronous Systems. ISCAS 1994: 283-286
1993
9EELiang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Mean Sha: Rotation Scheduling: A Loop Pipelining Algorithm. DAC 1993: 566-572
8 Liang-Fang Chao, Edwin Hsing-Mean Sha: Unified Static Scheduling on Various Models. ICPP 1993: 231-235
7 Liang-Fang Chao, Edwin Hsing-Mean Sha: Static Scheduling of Uniform Nested Loops. IPPS 1993: 254-258
6 Edwin Hsing-Mean Sha, Kenneth Steiglitz: Maintaining Bipartite Matchings in the Presence of Failures. IPPS 1993: 57-64
5 Edwin Hsing-Mean Sha, Kenneth Steiglitz: Reconfigurability and Reliability of Systolic/Wavefront Arrays. IEEE Trans. Computers 42(7): 854-862 (1993)
1992
4 Liang-Fang Chao, Edwin Hsing-Mean Sha: Retiming and Unfolding Data-Flow Graphs. ICPP (2) 1992: 33-40
3EEEdwin Hsing-Mean Sha, Kenneth Steiglitz: Error detection in arrays via dependency graphs. VLSI Signal Processing 4(4): 331-342 (1992)
1991
2 Edwin Hsing-Mean Sha, Liang-Fang Chao: Design for Easily Applying Test Vectors to Improve Delay Fault Coverage. ICCAD 1991: 500-503
1EEEdwin Hsing-Mean Sha, Kenneth Steiglitz: Explicit construction for reliable reconfigurable array architectures. SPDP 1991: 640-647

Coauthor Index

1Virgil Andronache [58]
2Steven C. Bass [11] [12] [15]
3Jiannong Cao [87] [88] [93] [118] [133]
4Keith C. C. Chan [118]
5Anantha Chandrakasan (Anantha P. Chandrakasan) [41]
6Liang-Fang Chao [2] [4] [7] [8] [9] [10] [16] [18] [19] [32] [33] [34]
7Fei Chen [45] [53]
8Kevin F. Chen [89] [90] [103] [105] [106] [107] [119] [132] [153]
9Wei Chen [109]
10Yen-Kuang Chen [140]
11Ying Chen [108]
12Jing Deng [146]
13Jiangfeng Ding [55]
14Jon C. Furgeson [55]
15Minyi Guo [139] [150]
16Sung-Kook Han [129]
17Yanxiang He [109]
18Yi He [82] [88] [91] [148]
19Bessie C. Hu [159]
20Jingtong Hu [141] [143] [145] [147] [148]
21Xiaobo Sharon Hu (Xiaobo Hu) [46] [47] [50] [51] [57] [60] [65]
22Shaoxiong Hua [142]
23Zhiping Jia [131]
24Yingtao Jiang [62]
25Roy Dz-Ching Ju (Roy Ju, Dz-Ching Ju) [37]
26Moon-hae Kim [129]
27Michael Kirkpatrick [56]
28Peter M. Kogge [43]
29Tei-Wei Kuo [139]
30Andrea S. LaPaugh [9] [32]
31Chenhua Lang [26]
32Su Te Lei [136]
33Hao Li [155]
34David W. Lin [140]
35Man Lin [142]
36Meilin Liu [89] [91] [95] [97] [99] [104] [105] [106] [110] [113] [114] [115] [117] [124] [125] [126] [127] [128] [137] [142] [151] [152] [158]
37Meiqin Liu [150]
38John V. McCanny [140]
39Timothy W. O'Neil [49] [53] [59] [64] [72] [74] [75] [100] [111] [120]
40Nelson L. Passos [11] [12] [13] [14] [15] [17] [18] [19] [20] [24] [25] [26] [27] [28] [30] [33] [36] [37] [38] [39] [40] [54] [58] [75] [83]
41Chantana Phongpensri (Chantana Chantrapornchai) [29] [36] [38] [39] [42] [43] [46] [48] [49] [50] [51] [54] [57] [68] [73] [77] [78] [96] [98] [121]
42Meikang Qiu (Mei Kang Qiu) [104] [110] [113] [114] [117] [122] [125] [126] [127] [128] [131] [135] [138] [141] [142] [143] [145] [146] [147] [148] [149] [150] [151] [152] [154] [155] [157] [158]
43Nicole Marie Sabine [22]
44Zili Shao [68] [71] [78] [79] [81] [82] [84] [86] [87] [89] [91] [92] [94] [95] [97] [99] [101] [102] [104] [105] [108] [110] [113] [114] [115] [116] [117] [118] [122] [123] [125] [126] [127] [128] [130] [131] [133] [134] [137] [138] [139] [144] [149] [151] [152] [156]
45Michael Sheliga [21] [23] [30]
46Kenneth Steiglitz [1] [3] [5] [6]
47Wanlop Surakampontorn [121]
48Wanlop Surakumpolthorn [96] [98]
49David R. Surma [31] [35] [52] [54] [83]
50Yi Tian [43]
51Sissades Tongsima [14] [17] [29] [36] [38] [39] [42] [48] [49] [54]
52Wei-Che Tseng [143] [145] [147]
53Kaisheng Wang [44]
54Meng Wang [134]
55Qingyan Wang [25]
56Yuke Wang [62] [66]
57Zhong Wang [56] [59] [61] [65] [66]
58Jiande Wu [145] [147] [148]
59Bin Xiao [63] [68] [69] [70] [73] [76] [79] [81] [85] [86] [87] [88] [93] [94] [95] [99] [102] [107] [108] [109] [116] [122] [123] [129] [133]
60Guoliang Xing [144] [156]
61Cathy Qun Xu [80] [143] [159]
62Cheng-Zhong Xu [129]
63Chun Jason Xue (Chun Xue) [86] [91] [94] [101] [102] [104] [105] [108] [110] [113] [114] [115] [116] [117] [118] [122] [123] [124] [125] [126] [127] [128] [130] [131] [134] [137] [138] [141] [143] [144] [145] [147] [149] [150] [151] [152] [156] [158] [159]
64Laurence Tianruo Yang [129] [139] [142] [150]
65Ted Zhihong Yu [37] [44]
66Zhaohui Yuan [144] [156]
67Kang Zhang [136]
68Lei Zhang [143] [157]
69Youtao Zhang [80] [84]
70Hai Zhao [22]
71Si-Qing Zheng (S. Q. Zheng) [103] [153]
72Tao Zhou [47] [60]
73Qingfeng Zhuge [61] [63] [68] [69] [70] [71] [73] [76] [77] [78] [79] [81] [82] [84] [85] [86] [87] [88] [89] [91] [92] [95] [97] [99] [101] [102] [104] [108] [110] [114] [116] [117] [122] [123] [127] [128] [133] [137] [141]

Colors in the list of coauthors

Copyright © Tue Nov 3 08:52:44 2009 by Michael Ley (ley@uni-trier.de)