| |
| * | 2009 | |
|---|---|---|
| 4 | EE | Daisaku Seto, Minoru Watanabe: An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture. ASP-DAC 2009: 117-118 |
| 2008 | ||
| 3 | EE | Mao Nakajima, Daisaku Seto, Minoru Watanabe: A 937.5 ns multi-context holographic configuration with a 30.75 mus retention time. IPDPS 2008: 1-6 |
| 2 | EE | Daisaku Seto, Minoru Watanabe: A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory. ISVLSI 2008: 511-514 |
| 1 | EE | Daisaku Seto, Minoru Watanabe: Analysis of retention time under multi-configuration on a DORGA. SoCC 2008: 131-134 |
| 1 | Mao Nakajima | [3] |
| 2 | Minoru Watanabe | [1] [2] [3] [4] |