Ulf Schlichtmann Vis

*	2009
26	EE	Bing Li, Ning Chen, Manuel Schmidt, Walter Schneider, Ulf Schlichtmann: On hierarchical statistical static timing analysis. DATE 2009: 1320-1325
25	EE	Ulf Schlichtmann, Manuel Schmidt, Harald Kinzelbach, Michael Pronath, Volker Glöckel, Manfred Dietrich, Uwe Eichler, Joachim Haase: Digital design at a crossroads How to make statistical design methodologies industrially relevant. DATE 2009: 1542-1547
	2008
24	EE	Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann: Sizing Rules for Bipolar Analog Circuit Design. DATE 2008: 140-145
23	EE	Martin Strasser, Michael Eick, Helmut Gräb, Ulf Schlichtmann, Frank M. Johannes: Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions. ICCAD 2008: 306-313
22	EE	Michael Pehl, Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann: A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters. ICCD 2008: 188-193
21	EE	Peter Spindler, Ulf Schlichtmann, Frank M. Johannes: Abacus: fast legalization of standard cell circuits with minimal movement. ISPD 2008: 47-53
20	EE	Bing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann: Static Timing Model Extraction for Combinational Circuits. PATMOS 2008: 156-166
19	EE	Walter Schneider, Manuel Schmidt, Bing Li, Ulf Schlichtmann: A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA. PATMOS 2008: 167-177
18	EE	Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann: The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2209-2222 (2008)
17	EE	Peter Spindler, Ulf Schlichtmann, Frank M. Johannes: Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1398-1411 (2008)
	2007
16	EE	Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann: Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming. DATE 2007: 75-80
15	EE	Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann: Pareto-Front Computation and Automatic Sizing of CPPLLs. ISQED 2007: 481-486
	2006
14	EE	Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann: A CPPLL hierarchical optimization methodology considering jitter, power and locking time. DAC 2006: 19-24
13	EE	Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, R. Sommer, Michael Pronath, Andreas Ripp: DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. DATE 2006: 387-392
12	EE	Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann: Fast evaluation of analog circuit structures by polytopal approximations. ISCAS 2006
	2005
11	EE	Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann: Deterministic approaches to analog performance space exploration (PSE). DAC 2005: 869-874
10		Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann: Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen. GI Jahrestagung (1) 2005: 334-338
	2004
9	EE	Christian Piguet, Jacques Gautier, Christoph Heer, Ian O'Connor, Ulf Schlichtmann: Extremely Low-Power Logic. DATE 2004: 656-663
8	EE	Ulf Schlichtmann: Design Methodology Innovations Address Manufacturing Technology Challenges: Power and Performance. DSD 2004: 52-59
	2002
7	EE	K. Brock, C. Edwards, R. Lannoo, Ulf Schlichtmann, Antun Domic, Jacques Benkoski, David Overhauser, M. Kliment: Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs. DATE 2002: 538-539
6	EE	Ulf Schlichtmann: Systems Are Made from Transistors: UDSM Technology Creates New Challenges for Library and IC Development. DSD 2002: 2-3
5	EE	Ulf Schlichtmann: Tomorrows High-Quality SoCs Require High-Quality Embedded Memories Today. ISQED 2002: 225-
	1999
4	EE	Bernd Wurth, Ulf Schlichtmann, Klaus Eckl, Kurt Antreich: Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 4(3): 313-350 (1999)
	1996
3	EE	Peter H. Schneider, Ulf Schlichtmann, Bernd Wurth: Fast Power Estimation of Large Circuits. IEEE Design & Test of Computers 13(1): 70-78 (1996)
	1994
2	EE	Peter H. Schneider, Kurt Antreich, Ulf Schlichtmann: A new power estimation technique with application to decomposition of Boolean functions for low power. EURO-DAC 1994: 388-393
	1992
1	EE	Ulf Schlichtmann, Franc Brglez, Michael Hermann: Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping. DAC 1992: 374-379

Coauthor Index

1	Kurt Antreich	[2] [4]
2	Jacques Benkoski	[7]
3	Jeanne Bickford	[13]
4	Franc Brglez	[1]
5	K. Brock	[7]
6	Markus Bühler	[13]
7	Ning Chen	[26]
8	Manfred Dietrich	[25]
9	Antun Domic	[7]
10	Klaus Eckl	[4]
11	C. Edwards	[7]
12	Uwe Eichler	[25]
13	Michael Eick	[23]
14	Jacques Gautier	[9]
15	Volker Gloeckel (Volker Glöckel)	[25]
16	Helmut E. Graeb (Helmut Gräb)	[10] [11] [12] [14] [15] [16] [18] [22] [23] [24]
17	Joachim Haase	[25]
18	Christoph Heer	[9]
19	Michael Hermann	[1]
20	Jason Hibbeler	[13]
21	Frank M. Johannes	[17] [21] [23]
22	Harald Kinzelbach	[25]
23	M. Kliment	[7]
24	Christoph Knoth	[20]
25	Jürgen Koehl	[13]
26	R. Lannoo	[7]
27	Bing Li	[19] [20] [26]
28	Tobias Massier	[18] [22] [24]
29	Daniel Mueller	[10] [11] [12] [14] [15] [16]
30	Ian O'Connor	[9]
31	David Overhauser	[7]
32	Michael Pehl	[22]
33	Christian Piguet	[9]
34	Michael Pronath	[13] [25]
35	Andreas Ripp	[13]
36	Manuel Schmidt	[19] [20] [25] [26]
37	Peter H. Schneider	[2] [3]
38	Walter Schneider	[19] [20] [26]
39	R. Sommer	[13]
40	Peter Spindler	[17] [21]
41	Guido Stehr	[10] [11] [12]
42	Martin Strasser	[23]
43	Bernd Wurth	[3] [4]
44	Jun Zou	[14] [15]

Colors in the list of coauthors