| * | 2004 |
|---|
| 7 | EE | Zaid Al-Ars,
Martin Herzog,
Ivo Schanstra,
A. J. van de Goor:
Influence of Bit Line Twisting on the Faulty Behavior of DRAMs.
MTDT 2004: 32-37 |
| 2003 |
|---|
| 6 | EE | Ivo Schanstra,
A. J. van de Goor:
Consequences of RAM Bitline Twisting for Test Coverage.
DATE 2003: 11176-11177 |
| 2002 |
|---|
| 5 | EE | A. J. van de Goor,
Ivo Schanstra:
Address and Data Scrambling: Causes and Impact on Memory Tests.
DELTA 2002: 128-136 |
| 1999 |
|---|
| 4 | | A. J. van de Goor,
Ivo Schanstra:
Industrial evaluation of stress combinations for march tests applied to SRAMs.
ITC 1999: 983-992 |
| 1998 |
|---|
| 3 | EE | Ivo Schanstra,
Dharmajaya Lukita,
A. J. van de Goor,
Kees Veelenturf,
Paul J. van Wijnen:
Semiconductor manufacturing process monitoring using built-in self-test for embedded memories.
ITC 1998: 872- |
| 1994 |
|---|
| 2 | | A. J. van de Goor,
Yervant Zorian,
Ivo Schanstra:
Functional Tests for Ring-Address SRAM-type FIFOs.
EDAC-ETC-EUROASIC 1994: 666 |
| 1 | | Yervant Zorian,
A. J. van de Goor,
Ivo Schanstra:
An Effective BIST Scheme for Ring-Address Type FIFOs.
ITC 1994: 378-387 |
